changedl.rpt

步进电机8细分CPLD相序及外部DA输出 实际细分数可达64细分 使用Atmel maxplus2 V10.1软件

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                 Logic cells placed in LAB 'B'
        +----------------------- LC28 DAT0
        | +--------------------- LC29 DAT1
        | | +------------------- LC21 DAT2
        | | | +----------------- LC19 DAT3
        | | | | +--------------- LC18 DAT4
        | | | | | +------------- LC17 DAT5
        | | | | | | +----------- LC27 DAT6
        | | | | | | | +--------- LC24 DAT7
        | | | | | | | | +------- LC22 DAT8
        | | | | | | | | | +----- LC30 DAT9
        | | | | | | | | | | +--- LC23 DAT10
        | | | | | | | | | | | +- LC26 DAT11
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':

Pin
4    -> * * * * * * * * * * * * | - * | <-- ADDR0
5    -> * * * * * * * * * * * * | - * | <-- ADDR1
6    -> * * * * * * * * * * * * | - * | <-- ADDR2
8    -> * * * * * * * * * * * * | - * | <-- ADDR3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                             f:\setup\changedl.rpt
changedl

** EQUATIONS **

ADDR0    : INPUT;
ADDR1    : INPUT;
ADDR2    : INPUT;
ADDR3    : INPUT;

-- Node name is 'DAT0' 
-- Equation name is 'DAT0', location is LC028, type is output.
 DAT0    = LCELL( _EQ001 $ !ADDR1);
  _EQ001 =  ADDR0 &  ADDR1 & !ADDR2 &  ADDR3
         #  ADDR0 & !ADDR1 & !ADDR2 & !ADDR3
         # !ADDR0 & !ADDR1 & !ADDR2 &  ADDR3
         #  ADDR0 & !ADDR1 &  ADDR3;

-- Node name is 'DAT1' 
-- Equation name is 'DAT1', location is LC029, type is output.
 DAT1    = LCELL( _EQ002 $  ADDR3);
  _EQ002 =  ADDR0 & !ADDR1 & !ADDR3
         # !ADDR1 &  ADDR3
         # !ADDR0 & !ADDR2;

-- Node name is 'DAT2' 
-- Equation name is 'DAT2', location is LC021, type is output.
 DAT2    = LCELL( _EQ003 $  VCC);
  _EQ003 =  ADDR0 &  ADDR1 & !ADDR2 &  ADDR3
         #  ADDR0 & !ADDR1 &  ADDR2 & !ADDR3
         # !ADDR0 & !ADDR1 & !ADDR2 &  ADDR3
         # !ADDR0 &  ADDR1;

-- Node name is 'DAT3' 
-- Equation name is 'DAT3', location is LC019, type is output.
 DAT3    = LCELL( _EQ004 $  VCC);
  _EQ004 = !ADDR0 & !ADDR1 & !ADDR2 &  ADDR3
         #  ADDR0 &  ADDR1 & !ADDR2
         #  ADDR0 & !ADDR1 &  ADDR2;

-- Node name is 'DAT4' 
-- Equation name is 'DAT4', location is LC018, type is output.
 DAT4    = LCELL( _EQ005 $ !ADDR3);
  _EQ005 = !ADDR0 & !ADDR1 &  ADDR2 & !ADDR3
         # !ADDR0 &  ADDR1 &  ADDR3
         #  ADDR0 &  ADDR2;

-- Node name is 'DAT5' 
-- Equation name is 'DAT5', location is LC017, type is output.
 DAT5    = LCELL( _EQ006 $  VCC);
  _EQ006 =  ADDR0 & !ADDR1 & !ADDR2 &  ADDR3
         #  ADDR1 &  ADDR2 & !ADDR3
         # !ADDR0 & !ADDR2 &  ADDR3;

-- Node name is 'DAT6' 
-- Equation name is 'DAT6', location is LC027, type is output.
 DAT6    = LCELL( _EQ007 $ !ADDR1);
  _EQ007 =  ADDR0 &  ADDR1 & !ADDR2 & !ADDR3
         #  ADDR0 & !ADDR1 &  ADDR2 & !ADDR3
         # !ADDR0 & !ADDR1 & !ADDR2 & !ADDR3
         #  ADDR0 & !ADDR1 & !ADDR2;

-- Node name is 'DAT7' 
-- Equation name is 'DAT7', location is LC024, type is output.
 DAT7    = LCELL( _EQ008 $  ADDR3);
  _EQ008 =  ADDR1 &  ADDR2 & !ADDR3
         # !ADDR0 &  ADDR2 &  ADDR3
         #  ADDR0 &  ADDR1;

-- Node name is 'DAT8' 
-- Equation name is 'DAT8', location is LC022, type is output.
 DAT8    = LCELL( _EQ009 $  VCC);
  _EQ009 =  ADDR0 & !ADDR1 &  ADDR2 &  ADDR3
         #  ADDR0 &  ADDR1 & !ADDR2 & !ADDR3
         # !ADDR0 & !ADDR1 & !ADDR2 & !ADDR3
         # !ADDR0 &  ADDR1;

-- Node name is 'DAT9' 
-- Equation name is 'DAT9', location is LC030, type is output.
 DAT9    = LCELL( _EQ010 $  VCC);
  _EQ010 = !ADDR0 & !ADDR1 & !ADDR2 & !ADDR3
         #  ADDR0 &  ADDR1 & !ADDR2
         #  ADDR0 & !ADDR1 &  ADDR2;

-- Node name is 'DAT10' 
-- Equation name is 'DAT10', location is LC023, type is output.
 DAT10   = LCELL( _EQ011 $  ADDR3);
  _EQ011 = !ADDR1 &  ADDR2 &  ADDR3
         # !ADDR0 &  ADDR1 & !ADDR3
         #  ADDR0 &  ADDR2;

-- Node name is 'DAT11' 
-- Equation name is 'DAT11', location is LC026, type is output.
 DAT11   = LCELL( _EQ012 $  ADDR3);
  _EQ012 =  ADDR0 &  ADDR1 & !ADDR2 & !ADDR3
         #  ADDR1 &  ADDR2 &  ADDR3
         #  ADDR2 & !ADDR3;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                      f:\setup\changedl.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = on
   Rules                                  = EPLD Rules


Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   Design Doctor                          00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 6,334K