📄 cout40.rpt
字号:
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\setup\cout40.rpt
cout40
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC32 ADDRESS0
| +----------------------------- LC24 ADDRESS1
| | +--------------------------- LC29 ADDRESS2
| | | +------------------------- LC30 AD0
| | | | +----------------------- LC31 AD1
| | | | | +--------------------- LC17 |LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node1
| | | | | | +------------------- LC20 |LPM_ADD_SUB:147|addcore:adder|addcore:adder0|result_node1
| | | | | | | +----------------- LC28 |LPM_ADD_SUB:147|addcore:adder|addcore:adder0|result_node2
| | | | | | | | +--------------- LC18 |LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | +------------- LC23 |LPM_ADD_SUB:213|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | | +----------- LC22 |LPM_ADD_SUB:213|addcore:adder|addcore:adder0|result_node2
| | | | | | | | | | | +--------- LC27 addr_temp2
| | | | | | | | | | | | +------- LC19 addr_temp1
| | | | | | | | | | | | | +----- LC21 addr_temp0
| | | | | | | | | | | | | | +--- LC25 add_temp1
| | | | | | | | | | | | | | | +- LC26 add_temp0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC17 -> - * - * * - - - - - - - * - * * | * * | <-- |LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node1
LC20 -> - - - - * - - - - - - - - - * - | - * | <-- |LPM_ADD_SUB:147|addcore:adder|addcore:adder0|result_node1
LC18 -> - * - * * - - - - - - - * - * * | * * | <-- |LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node1
LC23 -> - - - - * - - - - - - - - - * - | - * | <-- |LPM_ADD_SUB:213|addcore:adder|addcore:adder0|result_node1
LC19 -> - - - - - * - - * - - - - - - - | * * | <-- addr_temp1
LC21 -> * - - * * * - - * - - - - * * * | * * | <-- addr_temp0
LC25 -> - - - - * - * * - * * - - - * - | - * | <-- add_temp1
LC26 -> - - - * - - * * - * * - - - - * | - * | <-- add_temp0
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- CLK
4 -> - * * * * - - - - - - * * - * * | * * | <-- DIRCH
LC2 -> - - * * * - - - - - - * - - * * | * * | <-- |LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node2
LC1 -> - - * * * - - - - - - * - - * * | * * | <-- |LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node2
LC4 -> - - - - - - - * - - * - - - - - | * * | <-- add_temp2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\setup\cout40.rpt
cout40
** EQUATIONS **
CLK : INPUT;
DIRCH : INPUT;
-- Node name is 'ADDRESS0' = ':18'
-- Equation name is 'ADDRESS0', type is output
ADDRESS0 = DFFE( addr_temp0 $ VCC, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'ADDRESS1' = ':16'
-- Equation name is 'ADDRESS1', type is output
ADDRESS1 = DFFE( _EQ001 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = DIRCH & _LC017
# !DIRCH & _LC018;
-- Node name is 'ADDRESS2' = ':14'
-- Equation name is 'ADDRESS2', type is output
ADDRESS2 = DFFE( _EQ002 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = DIRCH & _LC002
# !DIRCH & _LC001;
-- Node name is 'ADDRESS3' = ':12'
-- Equation name is 'ADDRESS3', type is output
ADDRESS3 = DFFE( _EQ003 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = DIRCH & _LC008
# !DIRCH & _LC006;
-- Node name is ':26' = 'addr_temp0'
-- Equation name is 'addr_temp0', location is LC021, type is buried.
addr_temp0 = TFFE( VCC, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is ':25' = 'addr_temp1'
-- Equation name is 'addr_temp1', location is LC019, type is buried.
addr_temp1 = DFFE( _EQ004 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = DIRCH & _LC017
# !DIRCH & _LC018;
-- Node name is ':24' = 'addr_temp2'
-- Equation name is 'addr_temp2', location is LC027, type is buried.
addr_temp2 = DFFE( _EQ005 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = DIRCH & _LC002
# !DIRCH & _LC001;
-- Node name is ':23' = 'addr_temp3'
-- Equation name is 'addr_temp3', location is LC005, type is buried.
addr_temp3 = DFFE( _EQ006 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = DIRCH & _LC008
# !DIRCH & _LC006;
-- Node name is ':29' = 'add_temp0'
-- Equation name is 'add_temp0', location is LC026, type is buried.
add_temp0 = TFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = !addr_temp0 & !DIRCH & _LC001 & _LC018
# addr_temp0 & !DIRCH & !_LC001 & !_LC018
# DIRCH & !_LC002 & !_LC017;
-- Node name is ':28' = 'add_temp1'
-- Equation name is 'add_temp1', location is LC025, type is buried.
add_temp1 = TFFE(!_EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006;
_X001 = EXP(!addr_temp0 & add_temp1 & !DIRCH & _LC001 & _LC018 & !_LC023);
_X002 = EXP(!addr_temp0 & !add_temp1 & !DIRCH & _LC001 & _LC018 & _LC023);
_X003 = EXP( addr_temp0 & !add_temp1 & !DIRCH & !_LC001 & !_LC018 & _LC023);
_X004 = EXP( addr_temp0 & add_temp1 & !DIRCH & !_LC001 & !_LC018 & !_LC023);
_X005 = EXP(!add_temp1 & DIRCH & !_LC002 & !_LC017 & _LC020);
_X006 = EXP( add_temp1 & DIRCH & !_LC002 & !_LC017 & !_LC020);
-- Node name is ':27' = 'add_temp2'
-- Equation name is 'add_temp2', location is LC004, type is buried.
add_temp2 = TFFE(!_EQ009, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = _X007 & _X008 & _X009 & _X010 & _X011 & _X012;
_X007 = EXP(!addr_temp0 & add_temp2 & !DIRCH & _LC001 & _LC018 & !_LC022);
_X008 = EXP(!addr_temp0 & !add_temp2 & !DIRCH & _LC001 & _LC018 & _LC022);
_X009 = EXP( addr_temp0 & !add_temp2 & !DIRCH & !_LC001 & !_LC018 & _LC022);
_X010 = EXP( addr_temp0 & add_temp2 & !DIRCH & !_LC001 & !_LC018 & !_LC022);
_X011 = EXP(!add_temp2 & DIRCH & !_LC002 & !_LC017 & _LC028);
_X012 = EXP( add_temp2 & DIRCH & !_LC002 & !_LC017 & !_LC028);
-- Node name is 'AD0' = ':10'
-- Equation name is 'AD0', type is output
AD0 = DFFE( _EQ010 $ !add_temp0, GLOBAL( CLK), VCC, VCC, VCC);
_EQ010 = _X013 & _X014 & _X015 & _X016 & _X017 & _X018;
_X013 = EXP(!addr_temp0 & add_temp0 & !DIRCH & _LC001 & _LC018);
_X014 = EXP(!addr_temp0 & !add_temp0 & !DIRCH & _LC001 & _LC018);
_X015 = EXP( addr_temp0 & !add_temp0 & !DIRCH & !_LC001 & !_LC018);
_X016 = EXP( addr_temp0 & add_temp0 & !DIRCH & !_LC001 & !_LC018);
_X017 = EXP(!add_temp0 & DIRCH & !_LC002 & !_LC017);
_X018 = EXP( add_temp0 & DIRCH & !_LC002 & !_LC017);
-- Node name is 'AD1' = ':8'
-- Equation name is 'AD1', type is output
AD1 = DFFE( _EQ011 $ !add_temp1, GLOBAL( CLK), VCC, VCC, VCC);
_EQ011 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006;
_X001 = EXP(!addr_temp0 & add_temp1 & !DIRCH & _LC001 & _LC018 & !_LC023);
_X002 = EXP(!addr_temp0 & !add_temp1 & !DIRCH & _LC001 & _LC018 & _LC023);
_X003 = EXP( addr_temp0 & !add_temp1 & !DIRCH & !_LC001 & !_LC018 & _LC023);
_X004 = EXP( addr_temp0 & add_temp1 & !DIRCH & !_LC001 & !_LC018 & !_LC023);
_X005 = EXP(!add_temp1 & DIRCH & !_LC002 & !_LC017 & _LC020);
_X006 = EXP( add_temp1 & DIRCH & !_LC002 & !_LC017 & !_LC020);
-- Node name is 'AD2' = ':6'
-- Equation name is 'AD2', type is output
AD2 = DFFE( _EQ012 $ !add_temp2, GLOBAL( CLK), VCC, VCC, VCC);
_EQ012 = _X007 & _X008 & _X009 & _X010 & _X011 & _X012;
_X007 = EXP(!addr_temp0 & add_temp2 & !DIRCH & _LC001 & _LC018 & !_LC022);
_X008 = EXP(!addr_temp0 & !add_temp2 & !DIRCH & _LC001 & _LC018 & _LC022);
_X009 = EXP( addr_temp0 & !add_temp2 & !DIRCH & !_LC001 & !_LC018 & _LC022);
_X010 = EXP( addr_temp0 & add_temp2 & !DIRCH & !_LC001 & !_LC018 & !_LC022);
_X011 = EXP(!add_temp2 & DIRCH & !_LC002 & !_LC017 & _LC028);
_X012 = EXP( add_temp2 & DIRCH & !_LC002 & !_LC017 & !_LC028);
-- Node name is '|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC017', type is buried
_LC017 = LCELL( addr_temp0 $ addr_temp1);
-- Node name is '|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC002', type is buried
_LC002 = LCELL( _EQ013 $ addr_temp2);
_EQ013 = addr_temp0 & addr_temp1;
-- Node name is '|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC008', type is buried
_LC008 = LCELL(!addr_temp3 $ _EQ014);
_EQ014 = _X019;
_X019 = EXP( addr_temp0 & addr_temp1 & addr_temp2);
-- Node name is '|LPM_ADD_SUB:147|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( add_temp0 $ add_temp1);
-- Node name is '|LPM_ADD_SUB:147|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( _EQ015 $ add_temp2);
_EQ015 = add_temp0 & add_temp1;
-- Node name is '|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC018', type is buried
_LC018 = LCELL( addr_temp1 $ !addr_temp0);
-- Node name is '|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC001', type is buried
_LC001 = LCELL( _EQ016 $ !addr_temp2);
_EQ016 = addr_temp0
# addr_temp1;
-- Node name is '|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC006', type is buried
_LC006 = LCELL( _EQ017 $ !addr_temp3);
_EQ017 = addr_temp1
# addr_temp2
# addr_temp0;
-- Node name is '|LPM_ADD_SUB:213|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried
_LC023 = LCELL( add_temp1 $ !add_temp0);
-- Node name is '|LPM_ADD_SUB:213|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC022', type is buried
_LC022 = LCELL( _EQ018 $ !add_temp2);
_EQ018 = add_temp0
# add_temp1;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\setup\cout40.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = on
Rules = EPLD Rules
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
Design Doctor 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,798K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -