📄 cout.rpt
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_LC064 = TFFE( _EQ028, _EQ029, VCC, VCC, VCC);
_EQ028 = !dir & _LC038 & _LC039 & !_LC052
# !dir & !_LC038 & !_LC039 & _LC052
# dir & !_LC042 & !_LC044;
_EQ029 = clk & en2 & _LC004;
-- Node name is '|COUT40:322|:28' = '|COUT40:322|add_temp1'
-- Equation name is '_LC034', type is buried
_LC034 = TFFE(!_EQ030, _EQ031, VCC, VCC, VCC);
_EQ030 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006;
_X001 = EXP(!dir & _LC034 & _LC038 & _LC039 & !_LC052 & !_LC062);
_X002 = EXP(!dir & !_LC034 & _LC038 & _LC039 & !_LC052 & _LC062);
_X003 = EXP(!dir & !_LC034 & !_LC038 & !_LC039 & _LC052 & _LC062);
_X004 = EXP(!dir & _LC034 & !_LC038 & !_LC039 & _LC052 & !_LC062);
_X005 = EXP( dir & !_LC034 & !_LC042 & !_LC044 & _LC056);
_X006 = EXP( dir & _LC034 & !_LC042 & !_LC044 & !_LC056);
_EQ031 = clk & en2 & _LC004;
-- Node name is '|COUT40:322|:27' = '|COUT40:322|add_temp2'
-- Equation name is '_LC054', type is buried
_LC054 = TFFE(!_EQ032, _EQ033, VCC, VCC, VCC);
_EQ032 = _X007 & _X008 & _X009 & _X010 & _X011 & _X012;
_X007 = EXP(!dir & _LC038 & _LC039 & !_LC052 & _LC054 & !_LC055);
_X008 = EXP(!dir & _LC038 & _LC039 & !_LC052 & !_LC054 & _LC055);
_X009 = EXP(!dir & !_LC038 & !_LC039 & _LC052 & !_LC054 & _LC055);
_X010 = EXP(!dir & !_LC038 & !_LC039 & _LC052 & _LC054 & !_LC055);
_X011 = EXP( dir & !_LC042 & !_LC044 & !_LC054 & _LC061);
_X012 = EXP( dir & !_LC042 & !_LC044 & _LC054 & !_LC061);
_EQ033 = clk & en2 & _LC004;
-- Node name is '|COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC044', type is buried
_LC044 = LCELL( _EQ034 $ GND);
_EQ034 = !_LC052 & _LC058
# _LC052 & !_LC058;
-- Node name is '|COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC042', type is buried
_LC042 = LCELL( _EQ035 $ _LC063);
_EQ035 = _LC052 & _LC058;
-- Node name is '|COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC045', type is buried
_LC045 = LCELL(!_LC002 $ _EQ036);
_EQ036 = _X013;
_X013 = EXP( _LC052 & _LC058 & _LC063);
-- Node name is '|COUT40:322|LPM_ADD_SUB:147|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC056', type is buried
_LC056 = LCELL( _LC064 $ _LC034);
-- Node name is '|COUT40:322|LPM_ADD_SUB:147|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC061', type is buried
_LC061 = LCELL( _EQ037 $ _LC054);
_EQ037 = _LC034 & _LC064;
-- Node name is '|COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC038', type is buried
_LC038 = LCELL(!_LC052 $ _LC058);
-- Node name is '|COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC039', type is buried
_LC039 = LCELL( _EQ038 $ !_LC063);
_EQ038 = _LC052
# _LC058;
-- Node name is '|COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC047', type is buried
_LC047 = LCELL( _EQ039 $ !_LC002);
_EQ039 = _LC058
# _LC063
# _LC052;
-- Node name is '|COUT40:322|LPM_ADD_SUB:213|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC062', type is buried
_LC062 = LCELL( _LC034 $ !_LC064);
-- Node name is '|COUT40:322|LPM_ADD_SUB:213|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC055', type is buried
_LC055 = LCELL( _EQ040 $ !_LC054);
_EQ040 = _LC064
# _LC034;
-- Node name is '|COUT40:322|:6'
-- Equation name is '_LC053', type is buried
_LC053 = DFFE( _EQ041 $ !_LC054, _EQ042, VCC, VCC, VCC);
_EQ041 = _X007 & _X008 & _X009 & _X010 & _X011 & _X012;
_X007 = EXP(!dir & _LC038 & _LC039 & !_LC052 & _LC054 & !_LC055);
_X008 = EXP(!dir & _LC038 & _LC039 & !_LC052 & !_LC054 & _LC055);
_X009 = EXP(!dir & !_LC038 & !_LC039 & _LC052 & !_LC054 & _LC055);
_X010 = EXP(!dir & !_LC038 & !_LC039 & _LC052 & _LC054 & !_LC055);
_X011 = EXP( dir & !_LC042 & !_LC044 & !_LC054 & _LC061);
_X012 = EXP( dir & !_LC042 & !_LC044 & _LC054 & !_LC061);
_EQ042 = clk & en2 & _LC004;
-- Node name is '|COUT40:322|:8'
-- Equation name is '_LC043', type is buried
_LC043 = DFFE( _EQ043 $ !_LC034, _EQ044, VCC, VCC, VCC);
_EQ043 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006;
_X001 = EXP(!dir & _LC034 & _LC038 & _LC039 & !_LC052 & !_LC062);
_X002 = EXP(!dir & !_LC034 & _LC038 & _LC039 & !_LC052 & _LC062);
_X003 = EXP(!dir & !_LC034 & !_LC038 & !_LC039 & _LC052 & _LC062);
_X004 = EXP(!dir & _LC034 & !_LC038 & !_LC039 & _LC052 & !_LC062);
_X005 = EXP( dir & !_LC034 & !_LC042 & !_LC044 & _LC056);
_X006 = EXP( dir & _LC034 & !_LC042 & !_LC044 & !_LC056);
_EQ044 = clk & en2 & _LC004;
-- Node name is '|COUT40:322|:10'
-- Equation name is '_LC060', type is buried
_LC060 = DFFE( _EQ045 $ !_LC064, _EQ046, VCC, VCC, VCC);
_EQ045 = _X014 & _X015 & _X016 & _X017 & _X018 & _X019;
_X014 = EXP(!dir & _LC038 & _LC039 & !_LC052 & _LC064);
_X015 = EXP(!dir & _LC038 & _LC039 & !_LC052 & !_LC064);
_X016 = EXP(!dir & !_LC038 & !_LC039 & _LC052 & !_LC064);
_X017 = EXP(!dir & !_LC038 & !_LC039 & _LC052 & _LC064);
_X018 = EXP( dir & !_LC042 & !_LC044 & !_LC064);
_X019 = EXP( dir & !_LC042 & !_LC044 & _LC064);
_EQ046 = clk & en2 & _LC004;
-- Node name is '|COUT40:322|:12'
-- Equation name is '_LC009', type is buried
_LC009 = DFFE( _EQ047 $ GND, _EQ048, VCC, VCC, VCC);
_EQ047 = dir & _LC045
# !dir & _LC047;
_EQ048 = clk & en2 & _LC004;
-- Node name is '|COUT40:322|:14'
-- Equation name is '_LC057', type is buried
_LC057 = DFFE( _EQ049 $ GND, _EQ050, VCC, VCC, VCC);
_EQ049 = dir & _LC042
# !dir & _LC039;
_EQ050 = clk & en2 & _LC004;
-- Node name is '|COUT40:322|:16'
-- Equation name is '_LC059', type is buried
_LC059 = DFFE( _EQ051 $ GND, _EQ052, VCC, VCC, VCC);
_EQ051 = dir & !_LC052 & _LC058
# dir & _LC052 & !_LC058
# !dir & _LC038;
_EQ052 = clk & en2 & _LC004;
-- Node name is '|COUT40:322|:18'
-- Equation name is '_LC050', type is buried
_LC050 = DFFE( _LC052 $ VCC, _EQ053, VCC, VCC, VCC);
_EQ053 = clk & en2 & _LC004;
-- Node name is '|XXOUT:228|:4' = '|XXOUT:228|first'
-- Equation name is '_LC001', type is buried
_LC001 = DFFE( VCC $ GND, blclk, VCC, VCC, VCC);
-- Node name is '|XXOUT:228|:2'
-- Equation name is '_LC004', type is buried
_LC004 = DFFE( _LC001 $ GND, blclk, VCC, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\alin\2h050\step_up_8\cout.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = on
Rules = EPLD Rules
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
Design Doctor 00:00:01
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,082K
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