📄 cout.rpt
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LC9 -> - - - - - - - - - - * * * * * | - * * - | <-- |COUT40:322|:12
LC57 -> - - - - - - - - - - * * * * * | - * * - | <-- |COUT40:322|:14
LC59 -> - - - - - - - - - - * * * * * | - * * - | <-- |COUT40:322|:16
LC50 -> - - - - - - - - - - * * * * * | - * * - | <-- |COUT40:322|:18
LC2 -> - - - - * - - * - - - - - - - | - - * - | <-- |COUT40:322|addr_temp3
LC63 -> - - - * * - * * - - - - - - - | - - * - | <-- |COUT40:322|addr_temp2
LC58 -> - - * * * * * * - - - - - - - | - - * * | <-- |COUT40:322|addr_temp1
LC52 -> - - * * * * * * * * - - - - - | - - * * | <-- |COUT40:322|addr_temp0
LC4 -> * * - - - - - - * * - - - - - | * - * * | <-- |XXOUT:228|:2
LC13 -> * * - - - - - - - - - - - - - | - - * - | <-- Qb
LC8 -> * * - - - - - - * * - - - - - | * - * * | <-- en2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\alin\2h050\step_up_8\cout.rpt
cout
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC51 ADD0
| +----------------------------- LC49 ADD1
| | +--------------------------- LC56 |COUT40:322|LPM_ADD_SUB:147|addcore:adder|addcore:adder0|result_node1
| | | +------------------------- LC61 |COUT40:322|LPM_ADD_SUB:147|addcore:adder|addcore:adder0|result_node2
| | | | +----------------------- LC62 |COUT40:322|LPM_ADD_SUB:213|addcore:adder|addcore:adder0|result_node1
| | | | | +--------------------- LC55 |COUT40:322|LPM_ADD_SUB:213|addcore:adder|addcore:adder0|result_node2
| | | | | | +------------------- LC53 |COUT40:322|:6
| | | | | | | +----------------- LC60 |COUT40:322|:10
| | | | | | | | +--------------- LC57 |COUT40:322|:14
| | | | | | | | | +------------- LC59 |COUT40:322|:16
| | | | | | | | | | +----------- LC50 |COUT40:322|:18
| | | | | | | | | | | +--------- LC63 |COUT40:322|addr_temp2
| | | | | | | | | | | | +------- LC58 |COUT40:322|addr_temp1
| | | | | | | | | | | | | +----- LC52 |COUT40:322|addr_temp0
| | | | | | | | | | | | | | +--- LC54 |COUT40:322|add_temp2
| | | | | | | | | | | | | | | +- LC64 |COUT40:322|add_temp0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC61 -> - - - - - - * - - - - - - - * - | - - - * | <-- |COUT40:322|LPM_ADD_SUB:147|addcore:adder|addcore:adder0|result_node2
LC55 -> - - - - - - * - - - - - - - * - | - - - * | <-- |COUT40:322|LPM_ADD_SUB:213|addcore:adder|addcore:adder0|result_node2
LC53 -> * * - - - - - - - - - - - - - - | - - * * | <-- |COUT40:322|:6
LC60 -> * * - - - - - - - - - - - - - - | - - * * | <-- |COUT40:322|:10
LC58 -> - - - - - - - - - * - - * - - - | - - * * | <-- |COUT40:322|addr_temp1
LC52 -> - - - - - - * * - * * - * * * * | - - * * | <-- |COUT40:322|addr_temp0
LC54 -> - - - * - * * - - - - - - - * - | - - - * | <-- |COUT40:322|add_temp2
LC64 -> - - * * * * - * - - - - - - - * | - - - * | <-- |COUT40:322|add_temp0
Pin
40 -> - - - - - - - - - - - - - - - - | - - - - | <-- change
37 -> - - - - - - * * * * * * * * * * | * - * * | <-- clk
35 -> - - - - - - * * * * - * * - * * | * - * * | <-- dir
LC44 -> - - - - - - * * - - - - - - * * | - - * * | <-- |COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node1
LC42 -> - - - - - - * * * - - * - - * * | - - * * | <-- |COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node2
LC38 -> - - - - - - * * - * - - * - * * | - - * * | <-- |COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node1
LC39 -> - - - - - - * * * - - * - - * * | - - * * | <-- |COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node2
LC43 -> * * - - - - - - - - - - - - - - | - - * * | <-- |COUT40:322|:8
LC34 -> - - * * * * - - - - - - - - - - | - - * * | <-- |COUT40:322|add_temp1
LC4 -> * * - - - - * * * * * * * * * * | * - * * | <-- |XXOUT:228|:2
LC11 -> * * - - - - - - - - - - - - - - | - - - * | <-- Qa
LC8 -> * * - - - - * * * * * * * * * * | * - * * | <-- en2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\alin\2h050\step_up_8\cout.rpt
cout
** EQUATIONS **
achange : INPUT;
bchange : INPUT;
blch : INPUT;
blclk : INPUT;
change : INPUT;
clk : INPUT;
dir : INPUT;
en : INPUT;
sel0 : INPUT;
sel1 : INPUT;
sel2 : INPUT;
-- Node name is 'ADD0'
-- Equation name is 'ADD0', location is LC051, type is output.
ADD0 = LCELL( _EQ001 $ GND);
_EQ001 = en2 & _LC004 & _LC043 & !_LC053 & _LC060 & Qa
# en2 & _LC004 & !_LC043 & _LC053 & Qa;
-- Node name is 'ADD1'
-- Equation name is 'ADD1', location is LC049, type is output.
ADD1 = LCELL( _EQ002 $ GND);
_EQ002 = en2 & _LC004 & _LC043 & _LC053 & _LC060 & Qa
# en2 & _LC004 & !_LC043 & !_LC053 & Qa;
-- Node name is 'ADD2'
-- Equation name is 'ADD2', location is LC046, type is output.
ADD2 = LCELL( _EQ003 $ GND);
_EQ003 = en2 & _LC004 & _LC043 & !_LC053 & Qb
# en2 & _LC004 & !_LC053 & _LC060 & Qb;
-- Node name is 'ADD3'
-- Equation name is 'ADD3', location is LC041, type is output.
ADD3 = LCELL( _EQ004 $ GND);
_EQ004 = en2 & _LC004 & _LC043 & _LC053 & Qb
# en2 & _LC004 & _LC053 & _LC060 & Qb;
-- Node name is 'blcf'
-- Equation name is 'blcf', location is LC014, type is output.
blcf = LCELL( _EQ005 $ GND);
_EQ005 = blch & _LC003;
-- Node name is 'dat0'
-- Equation name is 'dat0', location is LC040, type is output.
dat0 = LCELL( _EQ006 $ !_LC059);
_EQ006 = _LC009 & _LC050 & !_LC057 & _LC059
# !_LC009 & _LC050 & !_LC057 & !_LC059
# _LC009 & !_LC050 & !_LC057 & !_LC059
# _LC009 & _LC050 & !_LC059;
-- Node name is 'dat1'
-- Equation name is 'dat1', location is LC037, type is output.
dat1 = LCELL( _EQ007 $ _LC009);
_EQ007 = !_LC009 & _LC050 & !_LC059
# _LC009 & !_LC059
# !_LC050 & !_LC057;
-- Node name is 'dat2'
-- Equation name is 'dat2', location is LC036, type is output.
dat2 = LCELL( _EQ008 $ VCC);
_EQ008 = _LC009 & _LC050 & !_LC057 & _LC059
# !_LC009 & _LC050 & _LC057 & !_LC059
# _LC009 & !_LC050 & !_LC057 & !_LC059
# !_LC050 & _LC059;
-- Node name is 'dat3'
-- Equation name is 'dat3', location is LC035, type is output.
dat3 = LCELL( _EQ009 $ VCC);
_EQ009 = _LC009 & !_LC050 & !_LC057 & !_LC059
# _LC050 & !_LC057 & _LC059
# _LC050 & _LC057 & !_LC059;
-- Node name is 'dat4'
-- Equation name is 'dat4', location is LC033, type is output.
dat4 = LCELL( _EQ010 $ !_LC009);
_EQ010 = !_LC009 & !_LC050 & _LC057 & !_LC059
# _LC009 & !_LC050 & _LC059
# _LC050 & _LC057;
-- Node name is 'dat5'
-- Equation name is 'dat5', location is LC017, type is output.
dat5 = LCELL( _EQ011 $ VCC);
_EQ011 = _LC009 & _LC050 & !_LC057 & !_LC059
# !_LC009 & _LC057 & _LC059
# _LC009 & !_LC050 & !_LC057;
-- Node name is 'dat6'
-- Equation name is 'dat6', location is LC019, type is output.
dat6 = LCELL( _EQ012 $ !_LC059);
_EQ012 = !_LC009 & _LC050 & !_LC057 & _LC059
# !_LC009 & _LC050 & _LC057 & !_LC059
# !_LC009 & !_LC050 & !_LC057 & !_LC059
# _LC050 & !_LC057 & !_LC059;
-- Node name is 'dat7'
-- Equation name is 'dat7', location is LC020, type is output.
dat7 = LCELL( _EQ013 $ _LC009);
_EQ013 = !_LC009 & _LC057 & _LC059
# _LC009 & !_LC050 & _LC057
# _LC050 & _LC059;
-- Node name is 'dat8'
-- Equation name is 'dat8', location is LC021, type is output.
dat8 = LCELL( _EQ014 $ VCC);
_EQ014 = _LC009 & _LC050 & _LC057 & !_LC059
# !_LC009 & _LC050 & !_LC057 & _LC059
# !_LC009 & !_LC050 & !_LC057 & !_LC059
# !_LC050 & _LC059;
-- Node name is 'dat9'
-- Equation name is 'dat9', location is LC024, type is output.
dat9 = LCELL( _EQ015 $ VCC);
_EQ015 = !_LC009 & !_LC050 & !_LC057 & !_LC059
# _LC050 & !_LC057 & _LC059
# _LC050 & _LC057 & !_LC059;
-- Node name is 'dat10'
-- Equation name is 'dat10', location is LC025, type is output.
dat10 = LCELL( _EQ016 $ _LC009);
_EQ016 = _LC009 & _LC057 & !_LC059
# !_LC009 & !_LC050 & _LC059
# _LC050 & _LC057;
-- Node name is 'dat11'
-- Equation name is 'dat11', location is LC030, type is output.
dat11 = LCELL( _EQ017 $ _LC009);
_EQ017 = !_LC009 & _LC050 & !_LC057 & _LC059
# _LC009 & _LC057 & _LC059
# !_LC009 & _LC057;
-- Node name is ':244' = 'en2'
-- Equation name is 'en2', location is LC008, type is buried.
en2 = DFFE( en $ GND, GLOBAL( change), VCC, VCC, VCC);
-- Node name is ':177' = 'Qa'
-- Equation name is 'Qa', location is LC011, type is buried.
Qa = DFFE( _EQ018 $ GND, GLOBAL( change), achange, VCC, VCC);
_EQ018 = en2 & _LC004;
-- Node name is ':178' = 'Qb'
-- Equation name is 'Qb', location is LC013, type is buried.
Qb = DFFE( _EQ019 $ GND, GLOBAL( change), bchange, VCC, VCC);
_EQ019 = en2 & _LC004;
-- Node name is ':220' = 'reset'
-- Equation name is 'reset', location is LC015, type is buried.
reset = DFFE( GND $ VCC, _EQ020, blclk, VCC, VCC);
_EQ020 = clk & en2 & _LC004;
-- Node name is '|BL:222|:3'
-- Equation name is '_LC003', type is buried
_LC003 = DFFE(!reset $ GND, !blclk, VCC, VCC, VCC);
-- Node name is '|COUT40:322|:26' = '|COUT40:322|addr_temp0'
-- Equation name is '_LC052', type is buried
_LC052 = TFFE( VCC, _EQ021, VCC, VCC, VCC);
_EQ021 = clk & en2 & _LC004;
-- Node name is '|COUT40:322|:25' = '|COUT40:322|addr_temp1'
-- Equation name is '_LC058', type is buried
_LC058 = DFFE( _EQ022 $ GND, _EQ023, VCC, VCC, VCC);
_EQ022 = dir & !_LC052 & _LC058
# dir & _LC052 & !_LC058
# !dir & _LC038;
_EQ023 = clk & en2 & _LC004;
-- Node name is '|COUT40:322|:24' = '|COUT40:322|addr_temp2'
-- Equation name is '_LC063', type is buried
_LC063 = DFFE( _EQ024 $ GND, _EQ025, VCC, VCC, VCC);
_EQ024 = dir & _LC042
# !dir & _LC039;
_EQ025 = clk & en2 & _LC004;
-- Node name is '|COUT40:322|:23' = '|COUT40:322|addr_temp3'
-- Equation name is '_LC002', type is buried
_LC002 = DFFE( _EQ026 $ GND, _EQ027, VCC, VCC, VCC);
_EQ026 = dir & _LC045
# !dir & _LC047;
_EQ027 = clk & en2 & _LC004;
-- Node name is '|COUT40:322|:29' = '|COUT40:322|add_temp0'
-- Equation name is '_LC064', type is buried
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