📄 cout.rpt
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Total input pins required: 11
Total fast input logic cells required: 0
Total output pins required: 17
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 48
Total flipflops required: 21
Total product terms required: 154
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 19
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: e:\alin\2h050\step_up_8\cout.rpt
cout
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
3 (4) (A) INPUT 0 0 0 0 0 0 1 achange
2 (5) (A) INPUT 0 0 0 0 0 0 1 bchange
6 (1) (A) INPUT 0 0 0 0 0 1 0 blch
5 (3) (A) INPUT 0 0 0 0 0 0 4 blclk
40 - - INPUT G 0 0 0 0 0 0 0 change
37 - - INPUT 0 0 0 0 0 0 15 clk
35 (64) (D) INPUT 0 0 0 0 0 0 12 dir
34 (62) (D) INPUT 0 0 0 0 0 0 1 en
33 (57) (D) INPUT 0 0 0 0 0 0 0 sel0
31 (53) (D) INPUT 0 0 0 0 0 0 0 sel1
30 (52) (D) INPUT 0 0 0 0 0 0 0 sel2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\alin\2h050\step_up_8\cout.rpt
cout
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
28 51 D OUTPUT t 0 0 0 0 6 0 0 ADD0
27 49 D OUTPUT t 0 0 0 0 6 0 0 ADD1
25 46 C OUTPUT t 0 0 0 0 6 0 0 ADD2
23 41 C OUTPUT t 0 0 0 0 6 0 0 ADD3
43 14 A OUTPUT t 0 0 0 1 1 0 0 blcf
22 40 C OUTPUT t 1 0 1 0 4 0 0 dat0
21 37 C OUTPUT t 0 0 0 0 4 0 0 dat1
20 36 C OUTPUT t 0 0 0 0 4 0 0 dat2
19 35 C OUTPUT t 0 0 0 0 4 0 0 dat3
18 33 C OUTPUT t 0 0 0 0 4 0 0 dat4
15 17 B OUTPUT t 0 0 0 0 4 0 0 dat5
14 19 B OUTPUT t 1 0 1 0 4 0 0 dat6
13 20 B OUTPUT t 0 0 0 0 4 0 0 dat7
12 21 B OUTPUT t 0 0 0 0 4 0 0 dat8
11 24 B OUTPUT t 0 0 0 0 4 0 0 dat9
10 25 B OUTPUT t 0 0 0 0 4 0 0 dat10
8 30 B OUTPUT t 0 0 0 0 4 0 0 dat11
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\alin\2h050\step_up_8\cout.rpt
cout
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(5) 3 A DFFE t 0 0 0 1 1 1 0 |BL:222|:3
- 44 C SOFT t 0 0 0 0 2 0 6 |COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node1
- 42 C SOFT t 0 0 0 0 3 0 8 |COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node2
- 45 C SOFT t 1 0 0 0 4 0 2 |COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node3
(32) 56 D SOFT t 0 0 0 0 2 0 2 |COUT40:322|LPM_ADD_SUB:147|addcore:adder|addcore:adder0|result_node1
- 61 D SOFT t 0 0 0 0 3 0 2 |COUT40:322|LPM_ADD_SUB:147|addcore:adder|addcore:adder0|result_node2
- 38 C SOFT t 0 0 0 0 2 0 8 |COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node1
- 39 C SOFT t 0 0 0 0 3 0 8 |COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node2
- 47 C SOFT t 0 0 0 0 4 0 2 |COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node3
(34) 62 D SOFT t 0 0 0 0 2 0 2 |COUT40:322|LPM_ADD_SUB:213|addcore:adder|addcore:adder0|result_node1
- 55 D SOFT t 0 0 0 0 3 0 2 |COUT40:322|LPM_ADD_SUB:213|addcore:adder|addcore:adder0|result_node2
(31) 53 D DFFE t 6 6 0 2 10 4 0 |COUT40:322|:6
- 43 C DFFE t 6 6 0 2 10 4 0 |COUT40:322|:8
- 60 D DFFE t 6 0 0 2 8 4 0 |COUT40:322|:10
- 9 A DFFE t 0 0 0 2 4 12 0 |COUT40:322|:12
(33) 57 D DFFE t 0 0 0 2 4 12 0 |COUT40:322|:14
- 59 D DFFE t 0 0 0 2 5 12 0 |COUT40:322|:16
- 50 D DFFE t 0 0 0 1 3 12 0 |COUT40:322|:18
- 2 A DFFE t 0 0 0 2 4 0 2 |COUT40:322|addr_temp3 (|COUT40:322|:23)
- 63 D DFFE t 0 0 0 2 4 0 4 |COUT40:322|addr_temp2 (|COUT40:322|:24)
- 58 D DFFE t 0 0 0 2 5 0 8 |COUT40:322|addr_temp1 (|COUT40:322|:25)
(30) 52 D TFFE t 0 0 0 1 2 0 15 |COUT40:322|addr_temp0 (|COUT40:322|:26)
- 54 D TFFE t 6 6 0 2 10 0 4 |COUT40:322|add_temp2 (|COUT40:322|:27)
- 34 C TFFE t 6 6 0 2 10 0 6 |COUT40:322|add_temp1 (|COUT40:322|:28)
(35) 64 D TFFE t 0 0 0 2 7 0 5 |COUT40:322|add_temp0 (|COUT40:322|:29)
(3) 4 A DFFE t 0 0 0 1 1 4 17 |XXOUT:228|:2
(6) 1 A DFFE t 0 0 0 1 0 0 1 |XXOUT:228|first (|XXOUT:228|:4)
(44) 11 A DFFE + t 0 0 0 1 2 2 0 Qa (:177)
- 13 A DFFE + t 0 0 0 1 2 2 0 Qb (:178)
- 15 A DFFE t 0 0 0 2 2 0 1 reset (:220)
(1) 8 A DFFE + t 0 0 0 1 0 4 17 en2 (:244)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\alin\2h050\step_up_8\cout.rpt
cout
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------- LC14 blcf
| +----------------- LC3 |BL:222|:3
| | +--------------- LC9 |COUT40:322|:12
| | | +------------- LC2 |COUT40:322|addr_temp3
| | | | +----------- LC4 |XXOUT:228|:2
| | | | | +--------- LC1 |XXOUT:228|first
| | | | | | +------- LC11 Qa
| | | | | | | +----- LC13 Qb
| | | | | | | | +--- LC15 reset
| | | | | | | | | +- LC8 en2
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | A B C D | Logic cells that feed LAB 'A':
LC3 -> * - - - - - - - - - | * - - - | <-- |BL:222|:3
LC4 -> - - * * - - * * * - | * - * * | <-- |XXOUT:228|:2
LC1 -> - - - - * - - - - - | * - - - | <-- |XXOUT:228|first
LC15 -> - * - - - - - - - - | * - - - | <-- reset
LC8 -> - - * * - - * * * - | * - * * | <-- en2
Pin
3 -> - - - - - - * - - - | * - - - | <-- achange
2 -> - - - - - - - * - - | * - - - | <-- bchange
6 -> * - - - - - - - - - | * - - - | <-- blch
5 -> - * - - * * - - * - | * - - - | <-- blclk
40 -> - - - - - - - - - - | - - - - | <-- change
37 -> - - * * - - - - * - | * - * * | <-- clk
35 -> - - * * - - - - - - | * - * * | <-- dir
34 -> - - - - - - - - - * | * - - - | <-- en
LC45 -> - - * * - - - - - - | * - - - | <-- |COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node3
LC47 -> - - * * - - - - - - | * - - - | <-- |COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\alin\2h050\step_up_8\cout.rpt
cout
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------- LC17 dat5
| +----------- LC19 dat6
| | +--------- LC20 dat7
| | | +------- LC21 dat8
| | | | +----- LC24 dat9
| | | | | +--- LC25 dat10
| | | | | | +- LC30 dat11
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'B'
LC | | | | | | | | A B C D | Logic cells that feed LAB 'B':
Pin
40 -> - - - - - - - | - - - - | <-- change
37 -> - - - - - - - | * - * * | <-- clk
LC9 -> * * * * * * * | - * * - | <-- |COUT40:322|:12
LC57 -> * * * * * * * | - * * - | <-- |COUT40:322|:14
LC59 -> * * * * * * * | - * * - | <-- |COUT40:322|:16
LC50 -> * * * * * * * | - * * - | <-- |COUT40:322|:18
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\alin\2h050\step_up_8\cout.rpt
cout
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC46 ADD2
| +--------------------------- LC41 ADD3
| | +------------------------- LC44 |COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node1
| | | +----------------------- LC42 |COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node2
| | | | +--------------------- LC45 |COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node3
| | | | | +------------------- LC38 |COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node1
| | | | | | +----------------- LC39 |COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node2
| | | | | | | +--------------- LC47 |COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node3
| | | | | | | | +------------- LC43 |COUT40:322|:8
| | | | | | | | | +----------- LC34 |COUT40:322|add_temp1
| | | | | | | | | | +--------- LC40 dat0
| | | | | | | | | | | +------- LC37 dat1
| | | | | | | | | | | | +----- LC36 dat2
| | | | | | | | | | | | | +--- LC35 dat3
| | | | | | | | | | | | | | +- LC33 dat4
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC44 -> - - - - - - - - * * - - - - - | - - * * | <-- |COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node1
LC42 -> - - - - - - - - * * - - - - - | - - * * | <-- |COUT40:322|LPM_ADD_SUB:120|addcore:adder|addcore:adder0|result_node2
LC38 -> - - - - - - - - * * - - - - - | - - * * | <-- |COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node1
LC39 -> - - - - - - - - * * - - - - - | - - * * | <-- |COUT40:322|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node2
LC43 -> * * - - - - - - - - - - - - - | - - * * | <-- |COUT40:322|:8
LC34 -> - - - - - - - - * * - - - - - | - - * * | <-- |COUT40:322|add_temp1
Pin
40 -> - - - - - - - - - - - - - - - | - - - - | <-- change
37 -> - - - - - - - - * * - - - - - | * - * * | <-- clk
35 -> - - - - - - - - * * - - - - - | * - * * | <-- dir
LC56 -> - - - - - - - - * * - - - - - | - - * - | <-- |COUT40:322|LPM_ADD_SUB:147|addcore:adder|addcore:adder0|result_node1
LC62 -> - - - - - - - - * * - - - - - | - - * - | <-- |COUT40:322|LPM_ADD_SUB:213|addcore:adder|addcore:adder0|result_node1
LC53 -> * * - - - - - - - - - - - - - | - - * * | <-- |COUT40:322|:6
LC60 -> * * - - - - - - - - - - - - - | - - * * | <-- |COUT40:322|:10
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