cout.rpt

步进电机8细分CPLD相序及外部DA输出 实际细分数可达64细分 使用Atmel maxplus2 V10.1软件

Project Information                           e:\alin\2h050\step_up_8\cout.rpt

MAX+plus II Compiler Report File
Version 10.12 09/21/2001
Compiled: 09/09/2008 08:40:45

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

cout      EPM7064STC44-10  11       17       0      48      19          75 %

User Pins:                 11       17       0  



Project Information                           e:\alin\2h050\step_up_8\cout.rpt

** PROJECT COMPILATION MESSAGES **

Design Doctor Warning: Multiple flipflops and/or synchronous memories drive Clock node (ID 'clk2')
Design Doctor Warning: Flipflop or synchronous memory '|BL:222|:3' receives data that is synchronized by another Clock at flipflop or synchronous memory 'reset'
Design Doctor Warning: Flipflop or synchronous memory 'Qa' receives data that is synchronized by another Clock at flipflop or synchronous memory '|XXOUT:228|:2'
Design Doctor Warning: Flipflop or synchronous memory 'Qb' receives data that is synchronized by another Clock at flipflop or synchronous memory '|XXOUT:228|:2'
Design Doctor Warning: Multi-level logic drives Reset node (ID 'achange1')
Design Doctor Warning: Multi-level logic drives Reset node (ID 'bchange1')
Design Doctor Warning: Unknown combinatorial feedback structure detected at primitive 'bchange1'
Design Doctor Warning: Unknown combinatorial feedback structure detected at primitive 'achange1'
Design Doctor Warning: Logic that drives primitive 'dat5' contains a static 1 hazard when '|COUT40:322|:14' = 1, '|COUT40:322|:16' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:12' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat5' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:16' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:14' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat5' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:14' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:16' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat5' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:14' = 1, '|COUT40:322|:16' = 1 and primitive '|COUT40:322|:18' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat4' contains a static 1 hazard when '|COUT40:322|:14' = 1, '|COUT40:322|:16' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:12' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat4' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:16' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:14' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat4' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:14' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:16' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat4' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:14' = 1, '|COUT40:322|:16' = 1 and primitive '|COUT40:322|:18' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat3' contains a static 1 hazard when '|COUT40:322|:14' = 1, '|COUT40:322|:16' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:12' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat3' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:16' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:14' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat3' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:14' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:16' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat3' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:14' = 1, '|COUT40:322|:16' = 1 and primitive '|COUT40:322|:18' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat2' contains a static 1 hazard when '|COUT40:322|:14' = 1, '|COUT40:322|:16' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:12' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat2' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:16' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:14' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat2' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:14' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:16' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat2' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:14' = 1, '|COUT40:322|:16' = 1 and primitive '|COUT40:322|:18' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat1' contains a static 1 hazard when '|COUT40:322|:14' = 1, '|COUT40:322|:16' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:12' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat1' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:16' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:14' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat1' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:14' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:16' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat1' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:14' = 1, '|COUT40:322|:16' = 1 and primitive '|COUT40:322|:18' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat0' contains a static 1 hazard when '|COUT40:322|:14' = 1, '|COUT40:322|:16' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:12' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat0' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:16' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:14' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat0' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:14' = 1, '|COUT40:322|:18' = 1 and primitive '|COUT40:322|:16' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'dat0' contains a static 1 hazard when '|COUT40:322|:12' = 1, '|COUT40:322|:14' = 1, '|COUT40:322|:16' = 1 and primitive '|COUT40:322|:18' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'ADD1' contains a static 1 hazard when 'Qa' = 1, 'en2' = 1, '|XXOUT:228|:2' = 1, '|COUT40:322|:8' = 1, '|COUT40:322|:10' = 1 and primitive '|COUT40:322|:6' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'ADD1' contains a static 1 hazard when 'Qa' = 1, 'en2' = 1, '|XXOUT:228|:2' = 1, '|COUT40:322|:6' = 1, '|COUT40:322|:10' = 1 and primitive '|COUT40:322|:8' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'ADD1' contains a static 1 hazard when 'Qa' = 1, 'en2' = 1, '|XXOUT:228|:2' = 1, '|COUT40:322|:6' = 1, '|COUT40:322|:8' = 1 and primitive '|COUT40:322|:10' changes -- hazard found before logic synthesis
Info: Design Doctor issued 35 warning message(s) with EPLD Rules
Info: Reserved unused input pin 'sel2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'sel1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'sel0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board


Project Information                           e:\alin\2h050\step_up_8\cout.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'change' chosen for auto global Clock


Project Information                           e:\alin\2h050\step_up_8\cout.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

cout@3                            achange
cout@28                           ADD0
cout@27                           ADD1
cout@25                           ADD2
cout@23                           ADD3
cout@2                            bchange
cout@43                           blcf
cout@6                            blch
cout@5                            blclk
cout@40                           change
cout@37                           clk
cout@22                           dat0
cout@21                           dat1
cout@20                           dat2
cout@19                           dat3
cout@18                           dat4
cout@15                           dat5
cout@14                           dat6
cout@13                           dat7
cout@12                           dat8
cout@11                           dat9
cout@10                           dat10
cout@8                            dat11
cout@35                           dir
cout@34                           en
cout@33                           sel0
cout@31                           sel1
cout@30                           sel2


Project Information                           e:\alin\2h050\step_up_8\cout.rpt

** FILE HIERARCHY **



|bl:222|
|xxout:228|
|cout40:322|
|cout40:322|lpm_add_sub:120|
|cout40:322|lpm_add_sub:120|addcore:adder|
|cout40:322|lpm_add_sub:120|addcore:adder|addcore:adder0|
|cout40:322|lpm_add_sub:120|altshift:result_ext_latency_ffs|
|cout40:322|lpm_add_sub:120|altshift:carry_ext_latency_ffs|
|cout40:322|lpm_add_sub:120|altshift:oflow_ext_latency_ffs|
|cout40:322|lpm_add_sub:147|
|cout40:322|lpm_add_sub:147|addcore:adder|
|cout40:322|lpm_add_sub:147|addcore:adder|addcore:adder0|
|cout40:322|lpm_add_sub:147|altshift:result_ext_latency_ffs|
|cout40:322|lpm_add_sub:147|altshift:carry_ext_latency_ffs|
|cout40:322|lpm_add_sub:147|altshift:oflow_ext_latency_ffs|
|cout40:322|lpm_add_sub:186|
|cout40:322|lpm_add_sub:186|addcore:adder|
|cout40:322|lpm_add_sub:186|addcore:adder|addcore:adder0|
|cout40:322|lpm_add_sub:186|altshift:result_ext_latency_ffs|
|cout40:322|lpm_add_sub:186|altshift:carry_ext_latency_ffs|
|cout40:322|lpm_add_sub:186|altshift:oflow_ext_latency_ffs|
|cout40:322|lpm_add_sub:213|
|cout40:322|lpm_add_sub:213|addcore:adder|
|cout40:322|lpm_add_sub:213|addcore:adder|addcore:adder0|
|cout40:322|lpm_add_sub:213|altshift:result_ext_latency_ffs|
|cout40:322|lpm_add_sub:213|altshift:carry_ext_latency_ffs|
|cout40:322|lpm_add_sub:213|altshift:oflow_ext_latency_ffs|
|changedl:323|
|cout8:325|


Device-Specific Information:                  e:\alin\2h050\step_up_8\cout.rpt
cout

***** Logic for device 'cout' compiled without errors.




Device: EPM7064STC44-10

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff

              R     R                          
              E     E                          
              S     S     c                    
              E     E     h                    
              R  b  R     a                    
              V  l  V  V  n  G  G  c  G  d     
              E  c  E  C  g  N  N  l  N  i  e  
              D  f  D  C  e  D  D  k  D  r  n  
            -----------------------------------_ 
          /  44 43 42 41 40 39 38 37 36 35 34   | 
    #TDI |  1                                33 | sel0 
 bchange |  2                                32 | #TDO 
 achange |  3                                31 | sel1 
     GND |  4                                30 | sel2 
   blclk |  5                                29 | VCC 
    blch |  6        EPM7064STC44-10         28 | ADD0 
    #TMS |  7                                27 | ADD1 
   dat11 |  8                                26 | #TCK 
     VCC |  9                                25 | ADD2 
   dat10 | 10                                24 | GND 
    dat9 | 11                                23 | ADD3 
         |_  12 13 14 15 16 17 18 19 20 21 22  _| 
           ------------------------------------ 
              d  d  d  d  G  V  d  d  d  d  d  
              a  a  a  a  N  C  a  a  a  a  a  
              t  t  t  t  D  C  t  t  t  t  t  
              8  7  6  5        4  3  2  1  0  
                                               
                                               
                                               
                                               


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:                  e:\alin\2h050\step_up_8\cout.rpt
cout

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    10/16( 62%)   6/ 8( 75%)   0/16(  0%)  14/36( 38%) 
B:    LC17 - LC32     7/16( 43%)   8/ 8(100%)   1/16(  6%)   4/36( 11%) 
C:    LC33 - LC48    15/16( 93%)   8/ 8(100%)   8/16( 50%)  23/36( 63%) 
D:    LC49 - LC64    16/16(100%)   8/ 8(100%)  12/16( 75%)  19/36( 52%) 


Total dedicated input pins used:                 2/4      ( 50%)
Total I/O pins used:                            30/32     ( 93%)
Total logic cells used:                         48/64     ( 75%)
Total shareable expanders used:                 19/64     ( 29%)
Total Turbo logic cells used:                   48/64     ( 75%)
Total shareable expanders not available (n/a):   2/64     (  3%)
Average fan-in:                                  4.89
Total fan-in:                                   235