📄 digbuf.lst
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496 ;----------------------------------------------------
497 ; Enable/Disable Interrupt Mask
498 ;
499 ; Use the following macros to enable/disable
500 ; bits in the Interrupt mask registers,
501 ; INT_MSK0, INT_MSK1 or INT_MSK3.
502 ;
503 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
504 ; M8C_EnableIntMask INT_MSKN, MASK
505 ;
506 ; where INT_MSKN is INT_MSK0, INT_MSK1 or INT_MSK3
507 ; and MASK is the bit set to enable or disable
508 ;----------------------------------------------------
509 ; Disable Interrupt Bit Mask(s)
510 macro M8C_DisableIntMask
511 and reg[@0], ~@1 ; disable specified interrupt enable bit
512 0000' endm
513
514 ; Enable Interrupt Bit Mask(s)
515 macro M8C_EnableIntMask
516 or reg[@0], @1 ; enable specified interrupt enable bit
517 0000' endm
518
519 ;----------------------------------------------------
520 ; Clear Posted Interrupt Flag Mask
521 ;
522 ; Use the following macros to clear the
523 ; bits in the Interrupt Clear registers,
524 ; INT_CLR0, INT_CLR1 or INT_CLR3.
525 ; Usage: M8C_ClearIntFlag INT_CLRN, MASK
526 ;
527 ; where INT_MSKN is INT_CLR0, INT_CLR1 or INT_CLR3
528 ; and MASK is the bit set to enable or disable
529 ;----------------------------------------------------
530 macro M8C_ClearIntFlag
531 mov reg[@0], ~@1 ; clear specified interrupt enable bit
532 0000' endm
533
534 ;----------------------------------------------------
535 ; Power-On Reset & WatchDog Timer Functions
536 ;----------------------------------------------------
537 macro M8C_EnableWatchDog
538 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
539 0000' endm
540
541 macro M8C_ClearWDT
542 mov reg[RES_WDT], 00h
543 0000' endm
544
545 macro M8C_ClearWDTAndSleep
546 mov reg[RES_WDT], 38h
547 0000' endm
548
549 ;----------------------------------------------------
550 ; CPU Stall for Analog PSoC Block Writes
551 ;----------------------------------------------------
552 macro M8C_Stall
553 or reg[ASY_CR], ASY_CR_SYNCEN
554 0000' endm
555
556 macro M8C_Unstall
557 and reg[ASY_CR], ~ASY_CR_SYNCEN
558 0000' endm
559
560 ;----------------------------------------------------
561 ; Sleep, CPU Stop & Software Reset
562 ;----------------------------------------------------
563 macro M8C_Sleep
564 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
565 ; The next instruction to be executed depends on the state of the
566 ; various interrupt enable bits. If some interrupts are enabled
567 ; and the global interrupts are disabled, the next instruction will
568 ; be the one that follows the invocation of this macro. If global
569 ; interrupts are also enabled then the next instruction will be
570 ; from the interrupt vector table. If no interrupts are enabled
571 ; then the CPU sleeps forever.
572 0000' endm
573
574 macro M8C_Stop
575 ; In general, you probably don't want to do this, but here's how:
576 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
577 ; Next instruction to be executed is located in the interrupt
578 ; vector table entry for Power-On Reset.
579 0000' endm
580
581 macro M8C_Reset
582 ; Restore CPU to the power-on reset state.
583 mov A, 0
584 SSC
585 ; Next non-supervisor instruction will be at interrupt vector 0.
586 0000' endm
587
588 ;----------------------------------------------------
589 ; ImageCraft Code Compressor Actions
590 ;----------------------------------------------------
591 ; Suspend Code Compressor
592 ; Must not span a RET or RETI instruction
593 ; without resuming code compression
594 macro Suspend_CodeCompressor
595 or F, 0
596 0000' endm
597
598 ; Resume Code Compression
599 macro Resume_CodeCompressor
600 add SP, 0
601 0000' endm
1 ;;*****************************************************************************
2 ;;*****************************************************************************
3 ;;
4 ;; FILENAME: Memory.inc
5 ;;
6 ;; DESCRIPTION: Memory Model and Stack Parameter Definitions for
7 ;; the 24xxx family of PSoC devices.
8 ;;
9 ;; LAST MODIFIED: June 17, 2004
10 ;;
11 ;;-----------------------------------------------------------------------------
12 ;; Copyright (c) Cypress MicroSystems 2004. All Rights Reserved.
13 ;;*****************************************************************************
14 ;;*****************************************************************************
15 ;
16 ;
17 ; ******** Define Memory Model and Stack parameters ********
18 ;
19 0000 IMAGECRAFT: equ 1
20 0000 HITECH: equ 2
21 0000 TOOLCHAIN: equ HITECH
22 0000 SYSTEM_LARGE_MEMORY_MODEL: equ 0
23 0000 SYSTEM_SMALL_MEMORY_MODEL: equ 1
24 0000 SYSTEM_STACK_PAGE: equ 0
25 0000 SYSTEM_STACK_PAGE_OFFSET: equ 0
26 0000 SYSTEM_TOOLS: equ 2
27 0000 SYSTEM_IDXPG_TRACKS_STK_PP: equ 0
28 0000 SYSTEM_IDXPG_TRACKS_IDX_PP: equ 1
29 0000 SYSTEM_MULTIPAGE_STACK: equ 0
30
31
32 ; ******* Function Class Definitions *******
33 ;
34 ; These definitions are used to describe RAM access patterns. They provide
35 ; documentation and they control prologue and epilogue macros that perform
36 ; the necessary housekeeping functions for a large memory model device like
37 ; the CY8C29x66.
38
39 0000 RAM_USE_CLASS_1: equ 1 ; PUSH, POP & I/O access
40 0000 RAM_USE_CLASS_2: equ 2 ; Indexed address mode on stack page
41 0000 RAM_USE_CLASS_3: equ 4 ; Indexed address mode to any page
42 0000 RAM_USE_CLASS_4: equ 8 ; Direct/Indirect address mode access
43
44
45 ; ******* Page Pointer Manipulation Macros *******
46 ;
47 ; Most of the following macros are conditionally compiled so they only
48 ; produce code if the large memory model is selected.
49
50 ;-----------------------------------------------
51 ; Set Stack Page Macro
52 ;-----------------------------------------------
53 ;
54 ; DESC: Modify STK_PP in the large or small memory Models.
55 ;
56 ; INPUT: Constant (e.g., SYSTEM_STACK_PAGE) that specifies the RAM page on
57 ; which stack operations like PUSH and POP store and retrieve their
58 ; data
59 ;
60 ; COST: 8 instruction cycles (in LMM only)
61
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