📄 digbuf.lst
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329 0000 DBB00FN: equ 20h ; Function Register (RW)
330 0000 DBB00IN: equ 21h ; Input Register (RW)
331 0000 DBB00OU: equ 22h ; Output Register (RW)
332
333 ; Digital PSoC block 01, Basic Type B
334 0000 DBB01FN: equ 24h ; Function Register (RW)
335 0000 DBB01IN: equ 25h ; Input Register (RW)
336 0000 DBB01OU: equ 26h ; Output Register (RW)
337
338 ; Digital PSoC block 02, Communications Type B
339 0000 DCB02FN: equ 28h ; Function Register (RW)
340 0000 DCB02IN: equ 29h ; Input Register (RW)
341 0000 DCB02OU: equ 2Ah ; Output Register (RW)
342
343 ; Digital PSoC block 03, Communications Type B
344 0000 DCB03FN: equ 2Ch ; Function Register (RW)
345 0000 DCB03IN: equ 2Dh ; Input Register (RW)
346 0000 DCB03OU: equ 2Eh ; Output Register (RW)
347
348 ;------------------------------------------------
349 ; System and Global Resource Registers
350 ; Note: Also see this address range in Bank 0.
351 ;------------------------------------------------
352
353 0000 CLK_CR0: equ 60h ; Analog Column Clock Select Register 0 (RW)
354 0000 CLK_CR0_ACOLUMN_1: equ 0Ch ; MASK: Specify clock for analog cloumn
355 0000 CLK_CR0_ACOLUMN_0: equ 03h ; MASK: Specify clock for analog cloumn
356
357 0000 CLK_CR1: equ 61h ; Analog Clock Source Select Register 1 (RW)
358 0000 CLK_CR1_SHDIS: equ 40h ; MASK: Sample and Hold Disable (all Columns)
359 0000 CLK_CR1_ACLK1: equ 38h ; MASK: Digital PSoC block for analog source
360 0000 CLK_CR1_ACLK2: equ 07h ; MASK: Digital PSoC block for analog source
361
362 0000 ABF_CR0: equ 62h ; Analog Output Buffer Control Register 0 (RW)
363 0000 ABF_CR0_ACOL1MUX: equ 80h ; MASK: Analog Column 1 Mux control
364 0000 ABF_CR0_ABUF1EN: equ 20h ; MASK: Enable ACol 1 analog buffer (P0[5])
365 0000 ABF_CR0_ABUF0EN: equ 08h ; MASK: Enable ACol 0 analog buffer (P0[3])
366 0000 ABF_CR0_BYPASS: equ 02h ; MASK: Bypass the analog buffers
367 0000 ABF_CR0_PWR: equ 01h ; MASK: High power mode on all analog buffers
368
369 0000 AMD_CR0: equ 63h ; Analog Modulator Control Register 0 (RW)
370 0000 AMD_CR0_AMOD2: equ 70h ; MASK: Modulation source for analog column 2
371 0000 AMD_CR0_AMOD0: equ 07h ; MASK: Modulation source for analog column 1
372
373 0000 AMD_CR1: equ 66h ; Analog Modulator Control Register 1 (RW)
374 0000 AMD_CR1_AMOD3: equ 70h ; MASK: Modulation ctrl for analog column 3
375 0000 AMD_CR1_AMOD1: equ 07h ; MASK: Modulation ctrl for analog column 1
376
377 0000 ALT_CR0: equ 67h ; Analog Look Up Table (LUT) Register 0 (RW)
378 0000 ALT_CR0_LUT1: equ F0h ; MASK: Look up table 1 selection
379 0000 ALT_CR0_LUT0: equ 0Fh ; MASK: Look up table 0 selection
380
381 0000 ALT_CR1: equ 68h ; Analog Look Up Table (LUT) Register 1 (RW)
382 0000 ALT_CR1_LUT3: equ F0h ; MASK: Look up table 3 selection
383 0000 ALT_CR1_LUT2: equ 0Fh ; MASK: Look up table 2 selection
384
385 0000 CLK_CR2: equ 69h ; Analog Clock Source Control Register 2 (RW)
386 0000 CLK_CR2_ACLK1R: equ 08h ; MASK: Analog Clock 1 selection range
387 0000 CLK_CR2_ACLK0R: equ 01h ; MASK: Analog Clock 0 selection range
388
389 ;------------------------------------------------
390 ; Global Digital Interconnects
391 ;------------------------------------------------
392
393 0000 GDI_O_IN: equ D0h ; Global Dig Interconnect Odd Inputs Reg (RW)
394 0000 GDI_E_IN: equ D1h ; Global Dig Interconnect Even Inputs Reg (RW)
395 0000 GDI_O_OU: equ D2h ; Global Dig Interconnect Odd Outputs Reg (RW)
396 0000 GDI_E_OU: equ D3h ; Global Dig Interconnect Even Outputs Reg (RW)
397
398 ;------------------------------------------------
399 ; Clock and System Control Registers
400 ;------------------------------------------------
401
402 0000 OSC_GO_EN: equ DDh ; Oscillator to Global Outputs Enable Register (RW)
403 0000 OSC_GOEN_SLPINT: equ 80h ; Enable Sleep Timer onto GOE[7]
404 0000 OSC_GOEN_VC3: equ 40h ; Enable VC3 onto GOE[6]
405 0000 OSC_GOEN_VC2: equ 20h ; Enable VC2 onto GOE[5]
406 0000 OSC_GOEN_VC1: equ 10h ; Enable VC1 onto GOE[4]
407 0000 OSC_GOEN_SYSCLKX2: equ 08h ; Enable 2X SysClk onto GOE[3]
408 0000 OSC_GOEN_SYSCLK: equ 04h ; Enable 1X SysClk onto GOE[2]
409 0000 OSC_GOEN_CLK24M: equ 02h ; Enable 24 MHz clock onto GOE[1]
410 0000 OSC_GOEN_CLK32K: equ 01h ; Enable 32 kHz clock onto GOE[0]
411
412 0000 OSC_CR4: equ DEh ; Oscillator Control Register 4 (RW)
413 0000 OSC_CR4_VC3: equ 03h ; MASK: System VC3 Clock source
414
415 0000 OSC_CR3: equ DFh ; Oscillator Control Register 3 (RW)
416
417 0000 OSC_CR0: equ E0h ; System Oscillator Control Register 0 (RW)
418 0000 OSC_CR0_32K_SELECT: equ 80h ; MASK: Enable/Disable External XTAL Osc
419 0000 OSC_CR0_PLL_MODE: equ 40h ; MASK: Enable/Disable PLL
420 0000 OSC_CR0_NO_BUZZ: equ 20h ; MASK: Bandgap always powered/BUZZ bandgap
421 0000 OSC_CR0_SLEEP: equ 18h ; MASK: Set Sleep timer freq/period
422 0000 OSC_CR0_SLEEP_512Hz: equ 00h ; Set sleep bits for 1.95ms period
423 0000 OSC_CR0_SLEEP_64Hz: equ 08h ; Set sleep bits for 15.6ms period
424 0000 OSC_CR0_SLEEP_8Hz: equ 10h ; Set sleep bits for 125ms period
425 0000 OSC_CR0_SLEEP_1Hz: equ 18h ; Set sleep bits for 1 sec period
426 0000 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
427 0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
428 0000 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
429 0000 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
430 0000 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
431 0000 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
432 0000 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
433 0000 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
434 0000 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
435
436 0000 OSC_CR1: equ E1h ; System VC1/VC2 Divider Control Register (RW)
437 0000 OSC_CR1_VC1: equ F0h ; MASK: System VC1 24MHz/External Clk divider
438 0000 OSC_CR1_VC2: equ 0Fh ; MASK: System VC2 24MHz/External Clk divider
439
440 0000 OSC_CR2: equ E2h ; Oscillator Control Register 2 (RW)
441 0000 OSC_CR2_PLLGAIN: equ 80h ; MASK: High/Low gain
442 0000 OSC_CR2_EXTCLKEN: equ 04h ; MASK: Enable/Disable External Clock
443 0000 OSC_CR2_IMODIS: equ 02h ; MASK: Enable/Disable System (IMO) Clock Net
444 0000 OSC_CR2_SYSCLKX2DIS: equ 01h ; MASK: Enable/Disable 48MHz clock source
445
446 0000 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
447 0000 VLT_CR_SMP: equ 80h ; MASK: Enable Switch Mode Pump
448 0000 VLT_CR_PORLEV: equ 30h ; MASK: Mask for Power on Reset level control
449 0000 VLT_CR_POR_LOW: equ 00h ; Lowest Precision Power-on Reset trip point
450 0000 VLT_CR_POR_MID: equ 10h ; Middle Precision Power-on Reset trip point
451 0000 VLT_CR_POR_HIGH: equ 20h ; Highest Precision Power-on Reset trip point
452 0000 VLT_CR_LVDTBEN: equ 08h ; MASK: Enable the CPU Throttle Back on LVD
453 0000 VLT_CR_VM: equ 07h ; MASK: Mask for Voltage Monitor level setting
454 0000 VLT_CR_3V0_POR: equ 00h ; -- deprecated symbols --
455 0000 VLT_CR_4V5_POR: equ 10h ; deprecated
456 0000 VLT_CR_4V75_POR: equ 20h ; deprecated
457 0000 VLT_CR_DISABLE: equ 30h ; deprecated
458
459 0000 VLT_CMP: equ E4h ; Voltage Monitor Comparators Register (R)
460 0000 VLT_CMP_PUMP: equ 04h ; MASK: Vcc below SMP trip level
461 0000 VLT_CMP_LVD: equ 02h ; MASK: Vcc below LVD trip level
462 0000 VLT_CMP_PPOR: equ 01h ; MASK: Vcc below PPOR trip level
463
464 0000 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (W)
465 0000 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (W)
466 0000 BDG_TR: equ EAh ; Band Gap Trim Register (W)
467 0000 ECO_TR: equ EBh ; External Oscillator Trim Register (W)
468
469 ;;=============================================================================
470 ;; M8C System Macros
471 ;; These macros should be used when their functions are needed.
472 ;;=============================================================================
473
474 ;----------------------------------------------------
475 ; Swapping Register Banks
476 ;----------------------------------------------------
477 macro M8C_SetBank0
478 and F, ~FLAG_XIO_MASK
479 0000' endm
480
481 macro M8C_SetBank1
482 or F, FLAG_XIO_MASK
483 0000' endm
484
485 ;----------------------------------------------------
486 ; Global Interrupt Enable/Disable
487 ;----------------------------------------------------
488 macro M8C_EnableGInt
489 or F, FLAG_GLOBAL_IE
490 0000' endm
491
492 macro M8C_DisableGInt
493 and F, ~FLAG_GLOBAL_IE
494 0000' endm
495
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