📄 pwm8_1.lis
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000B PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
000F PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00DR0: equ 20h ; data register 0 (#)
0021 DBB00DR1: equ 21h ; data register 1 (W)
0022 DBB00DR2: equ 22h ; data register 2 (RW)
0023 DBB00CR0: equ 23h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01DR0: equ 24h ; data register 0 (#)
0025 DBB01DR1: equ 25h ; data register 1 (W)
0026 DBB01DR2: equ 26h ; data register 2 (RW)
0027 DBB01CR0: equ 27h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 02, Communications Type B
0028 DCB02DR0: equ 28h ; data register 0 (#)
0029 DCB02DR1: equ 29h ; data register 1 (W)
002A DCB02DR2: equ 2Ah ; data register 2 (RW)
002B DCB02CR0: equ 2Bh ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 03, Communications Type B
002C DCB03DR0: equ 2Ch ; data register 0 (#)
002D DCB03DR1: equ 2Dh ; data register 1 (W)
002E DCB03DR2: equ 2Eh ; data register 2 (RW)
002F DCB03CR0: equ 2Fh ; control & status register 0 (#)
0000
0000 ;-------------------------------------
0000 ; Analog Resource Control Registers
0000 ;-------------------------------------
0060 AMX_IN: equ 60h ; Analog Input Multiplexor Control (RW)
000C AMX_IN_ACI1: equ 0Ch ; MASK: column 1 input mux
0003 AMX_IN_ACI0: equ 03h ; MASK: column 0 input mux
0000
0063 ARF_CR: equ 63h ; Analog Reference Control Register (RW)
0040 ARF_CR_HBE: equ 40h ; MASK: Bias level control
0038 ARF_CR_REF: equ 38h ; MASK: Analog Reference controls
0007 ARF_CR_REFPWR: equ 07h ; MASK: Analog Reference power
0004 ARF_CR_APWR: equ 04h ; MASK: use deprecated; see datasheet
0003 ARF_CR_SCPWR: equ 03h ; MASK: Switched Cap block power
0000
0064 CMP_CR0: equ 64h ; Analog Comparator Bus 0 Register (#)
0020 CMP_CR0_COMP1: equ 20h ; MASK: Column 1 comparator state (R)
0010 CMP_CR0_COMP0: equ 10h ; MASK: Column 0 comparator state (R)
0002 CMP_CR0_AINT1: equ 02h ; MASK: Column 1 interrupt source (RW)
0001 CMP_CR0_AINT0: equ 01h ; MASK: Column 0 interrupt source (RW)
0000
0065 ASY_CR: equ 65h ; Analog Synchronizaton Control (#)
0070 ASY_CR_SARCOUNT: equ 70h ; MASK: SAR support: resolution count (W)
0008 ASY_CR_SARSIGN: equ 08h ; MASK: SAR support: sign (RW)
0006 ASY_CR_SARCOL: equ 06h ; MASK: SAR support: column spec (RW)
0001 ASY_CR_SYNCEN: equ 01h ; MASK: Stall bit (RW)
0000
0066 CMP_CR1: equ 66h ; Analog Comparator Bus 1 Register (RW)
0020 CMP_CR1_ASYNCH1: equ 20h ; MASK: Column 1 comparator bus synch
0010 CMP_CR1_ASYNCH0: equ 10h ; MASK: Column 0 comparator bus synch
0000
0000 ;---------------------------------------------------
0000 ; Analog PSoC block Registers
0000 ;
0000 ; Note: the following registers are mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;---------------------------------------------------
0000
0000 ; Continuous Time PSoC block Type B Row 0 Col 0
0070 ACB00CR3: equ 70h ; Control register 3 (RW)
0071 ACB00CR0: equ 71h ; Control register 0 (RW)
0072 ACB00CR1: equ 72h ; Control register 1 (RW)
0073 ACB00CR2: equ 73h ; Control register 2 (RW)
0000
0000 ; Continuous Time PSoC block Type B Row 0 Col 1
0074 ACB01CR3: equ 74h ; Control register 3 (RW)
0075 ACB01CR0: equ 75h ; Control register 0 (RW)
0076 ACB01CR1: equ 76h ; Control register 1 (RW)
0077 ACB01CR2: equ 77h ; Control register 2 (RW)
0000
0000 ; Switched Cap PSoC blockType C Row 1 Col 0
0080 ASC10CR0: equ 80h ; Control register 0 (RW)
0081 ASC10CR1: equ 81h ; Control register 1 (RW)
0082 ASC10CR2: equ 82h ; Control register 2 (RW)
0083 ASC10CR3: equ 83h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType D Row 1 Col 1
0084 ASD11CR0: equ 84h ; Control register 0 (RW)
0085 ASD11CR1: equ 85h ; Control register 1 (RW)
0086 ASD11CR2: equ 86h ; Control register 2 (RW)
0087 ASD11CR3: equ 87h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType D Row 2 Col 0
0090 ASD20CR0: equ 90h ; Control register 0 (RW)
0091 ASD20CR1: equ 91h ; Control register 1 (RW)
0092 ASD20CR2: equ 92h ; Control register 2 (RW)
0093 ASD20CR3: equ 93h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType C Row 2 Col 1
0094 ASC21CR0: equ 94h ; Control register 0 (RW)
0095 ASC21CR1: equ 95h ; Control register 1 (RW)
0096 ASC21CR2: equ 96h ; Control register 2 (RW)
0097 ASC21CR3: equ 97h ; Control register 3 (RW)
0000
0000 ;------------------------------------------------
0000 ; Row Digital Interconnects
0000 ;
0000 ; Note: the following registers are mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;------------------------------------------------
0000
00B0 RDI0RI: equ B0h ; Row Digital Interconnect Row 0 Input Reg (RW)
00B1 RDI0SYN: equ B1h ; Row Digital Interconnect Row 0 Sync Reg (RW)
00B2 RDI0IS: equ B2h ; Row 0 Input Select Register (RW)
00B3 RDI0LT0: equ B3h ; Row 0 Look Up Table Register 0 (RW)
00B4 RDI0LT1: equ B4h ; Row 0 Look Up Table Register 1 (RW)
00B5 RDI0RO0: equ B5h ; Row 0 Output Register 0 (RW)
00B6 RDI0RO1: equ B6h ; Row 0 Output Register 1 (RW)
0000
0000 ;------------------------------------------------
0000 ; I2C Configuration Registers
0000 ;------------------------------------------------
00D6 I2C_CFG: equ D6h ; I2C Configuration Register (RW)
0040 I2C_CFG_PINSEL: equ 40h ; MASK: Select P1[0] and P1[1] for I2C
0020 I2C_CFG_BUSERR_IE: equ 20h ; MASK: Enable interrupt on Bus Error
0010 I2C_CFG_STOP_IE: equ 10h ; MASK: Enable interrupt on Stop
0000 I2C_CFG_CLK_RATE_100K: equ 00h ; MASK: I2C clock set at 100K
0004 I2C_CFG_CLK_RATE_400K: equ 04h ; MASK: I2C clock set at 400K
0008 I2C_CFG_CLK_RATE_50K: equ 08h ; MASK: I2C clock set at 50K
000C I2C_CFG_CLK_RATE_1M6: equ 0Ch ; MASK: I2C clock set at 1.6M
000C I2C_CFG_CLK_RATE: equ 0Ch ; MASK: I2C clock rate setting mask
0002 I2C_CFG_PSELECT_MASTER: equ 02h ; MASK: Enable I2C Master
0001 I2C_CFG_PSELECT_SLAVE: equ 01h ; MASK: Enable I2C Slave
0000
00D7 I2C_SCR: equ D7h ; I2C Status and Control Register (#)
0080 I2C_SCR_BUSERR: equ 80h ; MASK: I2C Bus Error detected (RC)
0040 I2C_SCR_LOSTARB: equ 40h ; MASK: I2C Arbitration lost (RC)
0020 I2C_SCR_STOP: equ 20h ; MASK: I2C Stop detected (RC)
0010 I2C_SCR_ACK: equ 10h ; MASK: ACK the last byte (RW)
0008 I2C_SCR_ADDR: equ 08h ; MASK: Address rcv'd is Slave address (RC)
0004 I2C_SCR_XMIT: equ 04h ; MASK: Set transfer to tranmit mode (RW)
0002 I2C_SCR_LRB: equ 02h ; MASK: Last recieved bit (RC)
0001 I2C_SCR_BYTECOMPLETE: equ 01h ; MASK: Transfer of byte complete (RC)
0000
00D8 I2C_DR: equ D8h ; I2C Data Register (RW)
0000
00D9 I2C_MSCR: equ D9h ; I2C Master Status and Control Register (#)
0008 I2C_MSCR_BUSY: equ 08h ; MASK: I2C Busy (Start detected) (R)
0004 I2C_MSCR_MODE: equ 04h ; MASK: Start has been generated (R)
0002 I2C_MSCR_RESTART: equ 02h ; MASK: Generate a Restart condition (RW)
0001 I2C_MSCR_START: equ 01h ; MASK: Generate a Start condition (RW)
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ;------------------------------------------------
00DA INT_CLR0: equ DAh ; Interrupt Clear Register 0 (RW)
0000 ; Use INT_MSK0 bit field masks
00DB INT_CLR1: equ DBh ; Interrupt Clear Register 1 (RW)
0000 ; Use INT_MSK1 bit field masks
00DD INT_CLR3: equ DDh ; Interrupt Clear Register 3 (RW)
0000 ; Use INT_MSK3 bit field masks
0000
00DE INT_MSK3: equ DEh ; I2C and Software Mask Register (RW)
0080 INT_MSK3_ENSWINT: equ 80h ; MASK: enable/disable SW interrupt
0001 INT_MSK3_I2C: equ 01h ; MASK: enable/disable I2C interrupt
0000
00E0 INT_MSK0: equ E0h ; General Interrupt Mask Register (RW)
0080 INT_MSK0_VC3: equ 80h ; MASK: enable/disable VC3 interrupt
0040 INT_MSK0_SLEEP: equ 40h ; MASK: enable/disable sleep interrupt
0020 INT_MSK0_GPIO: equ 20h ; MASK: enable/disable GPIO interrupt
0004 INT_MSK0_ACOLUMN_1: equ 04h ; MASK: enable/disable Analog col 1 interrupt
0002 INT_MSK0_ACOLUMN_0: equ 02h ; MASK: enable/disable Analog col 0 interrupt
0001 INT_MSK0_VOLTAGE_MONITOR: equ 01h ; MASK: enable/disable Volts interrupt
0000
00E1 INT_MSK1: equ E1h ; Digital PSoC block Mask Register (RW)
0008 INT_MSK1_DCB03: equ 08h ; MASK: enable/disable DCB03 block interrupt
0004 INT_MSK1_DCB02: equ 04h ; MASK: enable/disable DCB02 block interrupt
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