📄 pwm8_1.lis
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0000 ;;*****************************************************************************
0000 ;;*****************************************************************************
0000 ;; FILENAME: PWM8_1.asm
0000 ;; Version: 2.5, Updated on 2006/05/15 at 15:09:31
0000 ;; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
0000 ;;
0000 ;; DESCRIPTION: PWM8 User Module software implementation file
0000 ;; for the 22/24/27/29xxx PSoC family of devices
0000 ;;
0000 ;; NOTE: User Module APIs conform to the fastcall16 convention for marshalling
0000 ;; arguments and observe the associated "Registers are volatile" policy.
0000 ;; This means it is the caller's responsibility to preserve any values
0000 ;; in the X and A registers that are still needed after the API functions
0000 ;; returns. For Large Memory Model devices it is also the caller's
0000 ;; responsibility to perserve any value in the CUR_PP, IDX_PP, MVR_PP and
0000 ;; MVW_PP registers. Even though some of these registers may not be modified
0000 ;; now, there is no guarantee that will remain the case in future releases.
0000 ;;-----------------------------------------------------------------------------
0000 ;; Copyright (c) Cypress MicroSystems 2000-2004. All Rights Reserved.
0000 ;;*****************************************************************************
0000 ;;*****************************************************************************
0000
0010 FLAG_XIO_MASK: equ 10h
0008 FLAG_SUPER: equ 08h
0004 FLAG_CARRY: equ 04h
0002 FLAG_ZERO: equ 02h
0001 FLAG_GLOBAL_IE: equ 01h
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 0
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
0002 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
0003 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
0000 ; Port 1
0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
0006 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
0007 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
0000 ; Port 2
0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
000B PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
000F PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00DR0: equ 20h ; data register 0 (#)
0021 DBB00DR1: equ 21h ; data register 1 (W)
0022 DBB00DR2: equ 22h ; data register 2 (RW)
0023 DBB00CR0: equ 23h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01DR0: equ 24h ; data register 0 (#)
0025 DBB01DR1: equ 25h ; data register 1 (W)
0026 DBB01DR2: equ 26h ; data register 2 (RW)
0027 DBB01CR0: equ 27h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 02, Communications Type B
0028 DCB02DR0: equ 28h ; data register 0 (#)
0029 DCB02DR1: equ 29h ; data register 1 (W)
002A DCB02DR2: equ 2Ah ; data register 2 (RW)
002B DCB02CR0: equ 2Bh ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 03, Communications Type B
002C DCB03DR0: equ 2Ch ; data register 0 (#)
002D DCB03DR1: equ 2Dh ; data register 1 (W)
002E DCB03DR2: equ 2Eh ; data register 2 (RW)
002F DCB03CR0: equ 2Fh ; control & status register 0 (#)
0000
0000 ;-------------------------------------
0000 ; Analog Resource Control Registers
0000 ;-------------------------------------
0060 AMX_IN: equ 60h ; Analog Input Multiplexor Control (RW)
000C AMX_IN_ACI1: equ 0Ch ; MASK: column 1 input mux
0003 AMX_IN_ACI0: equ 03h ; MASK: column 0 input mux
0000
0063 ARF_CR: equ 63h ; Analog Reference Control Register (RW)
0040 ARF_CR_HBE: equ 40h ; MASK: Bias level control
0038 ARF_CR_REF: equ 38h ; MASK: Analog Reference controls
0007 ARF_CR_REFPWR: equ 07h ; MASK: Analog Reference power
0004 ARF_CR_APWR: equ 04h ; MASK: use deprecated; see datasheet
0003 ARF_CR_SCPWR: equ 03h ; MASK: Switched Cap block power
0000
0064 CMP_CR0: equ 64h ; Analog Comparator Bus 0 Register (#)
0020 CMP_CR0_COMP1: equ 20h ; MASK: Column 1 comparator state (R)
0010 CMP_CR0_COMP0: equ 10h ; MASK: Column 0 comparator state (R)
0002 CMP_CR0_AINT1: equ 02h ; MASK: Column 1 interrupt source (RW)
0001 CMP_CR0_AINT0: equ 01h ; MASK: Column 0 interrupt source (RW)
0000
0065 ASY_CR: equ 65h ; Analog Synchronizaton Control (#)
0070 ASY_CR_SARCOUNT: equ 70h ; MASK: SAR support: resolution count (W)
0008 ASY_CR_SARSIGN: equ 08h ; MASK: SAR support: sign (RW)
0006 ASY_CR_SARCOL: equ 06h ; MASK: SAR support: column spec (RW)
0001 ASY_CR_SYNCEN: equ 01h ; MASK: Stall bit (RW)
0000
0066 CMP_CR1: equ 66h ; Analog Comparator Bus 1 Register (RW)
0020 CMP_CR1_ASYNCH1: equ 20h ; MASK: Column 1 comparator bus synch
0010 CMP_CR1_ASYNCH0: equ 10h ; MASK: Column 0 comparator bus synch
0000
0000 ;---------------------------------------------------
0000 ; Analog PSoC block Registers
0000 ;
0000 ; Note: the following registers are mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;---------------------------------------------------
0000
0000 ; Continuous Time PSoC block Type B Row 0 Col 0
0070 ACB00CR3: equ 70h ; Control register 3 (RW)
0071 ACB00CR0: equ 71h ; Control register 0 (RW)
0072 ACB00CR1: equ 72h ; Control register 1 (RW)
0073 ACB00CR2: equ 73h ; Control register 2 (RW)
0000
0000 ; Continuous Time PSoC block Type B Row 0 Col 1
0074 ACB01CR3: equ 74h ; Control register 3 (RW)
0075 ACB01CR0: equ 75h ; Control register 0 (RW)
0076 ACB01CR1: equ 76h ; Control register 1 (RW)
0077 ACB01CR2: equ 77h ; Control register 2 (RW)
0000
0000 ; Switched Cap PSoC blockType C Row 1 Col 0
0080 ASC10CR0: equ 80h ; Control register 0 (RW)
0081 ASC10CR1: equ 81h ; Control register 1 (RW)
0082 ASC10CR2: equ 82h ; Control register 2 (RW)
0083 ASC10CR3: equ 83h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType D Row 1 Col 1
0084 ASD11CR0: equ 84h ; Control register 0 (RW)
0085 ASD11CR1: equ 85h ; Control register 1 (RW)
0086 ASD11CR2: equ 86h ; Control register 2 (RW)
0087 ASD11CR3: equ 87h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType D Row 2 Col 0
0090 ASD20CR0: equ 90h ; Control register 0 (RW)
0091 ASD20CR1: equ 91h ; Control register 1 (RW)
0092 ASD20CR2: equ 92h ; Control register 2 (RW)
0093 ASD20CR3: equ 93h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType C Row 2 Col 1
0094 ASC21CR0: equ 94h ; Control register 0 (RW)
0095 ASC21CR1: equ 95h ; Control register 1 (RW)
0096 ASC21CR2: equ 96h ; Control register 2 (RW)
0097 ASC21CR3: equ 97h ; Control register 3 (RW)
0000
0000 ;------------------------------------------------
0000 ; Row Digital Interconnects
0000 ;
0000 ; Note: the following registers are mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;------------------------------------------------
0000
00B0 RDI0RI: equ B0h ; Row Digital Interconnect Row 0 Input Reg (RW)
00B1 RDI0SYN: equ B1h ; Row Digital Interconnect Row 0 Sync Reg (RW)
00B2 RDI0IS: equ B2h ; Row 0 Input Select Register (RW)
00B3 RDI0LT0: equ B3h ; Row 0 Look Up Table Register 0 (RW)
00B4 RDI0LT1: equ B4h ; Row 0 Look Up Table Register 1 (RW)
00B5 RDI0RO0: equ B5h ; Row 0 Output Register 0 (RW)
00B6 RDI0RO1: equ B6h ; Row 0 Output Register 1 (RW)
0000
0000 ;------------------------------------------------
0000 ; I2C Configuration Registers
0000 ;------------------------------------------------
00D6 I2C_CFG: equ D6h ; I2C Configuration Register (RW)
0040 I2C_CFG_PINSEL: equ 40h ; MASK: Select P1[0] and P1[1] for I2C
0020 I2C_CFG_BUSERR_IE: equ 20h ; MASK: Enable interrupt on Bus Error
0010 I2C_CFG_STOP_IE: equ 10h ; MASK: Enable interrupt on Stop
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