📄 pwm.lst
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47 ; Port 0
48 0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
49 0000 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
50 0000 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
51 0000 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
52 ; Port 1
53 0000 PRT1DR: equ 04h ; Port 1 Data Register (RW)
54 0000 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
55 0000 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
56 0000 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
57 ; Port 2
58 0000 PRT2DR: equ 08h ; Port 2 Data Register (RW)
59 0000 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
60 0000 PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
61 0000 PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
62 ; Port 3
63 0000 PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
64 0000 PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
65 0000 PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
66 0000 PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
67
68 ;------------------------------------------------
69 ; Digital PSoC(tm) block Registers
70 ; Note: Also see this address range in Bank 1.
71 ;------------------------------------------------
72 ; Digital PSoC block 00, Basic Type B
73 0000 DBB00DR0: equ 20h ; data register 0 (#)
74 0000 DBB00DR1: equ 21h ; data register 1 (W)
75 0000 DBB00DR2: equ 22h ; data register 2 (RW)
76 0000 DBB00CR0: equ 23h ; control & status register 0 (#)
77
78 ; Digital PSoC block 01, Basic Type B
79 0000 DBB01DR0: equ 24h ; data register 0 (#)
80 0000 DBB01DR1: equ 25h ; data register 1 (W)
81 0000 DBB01DR2: equ 26h ; data register 2 (RW)
82 0000 DBB01CR0: equ 27h ; control & status register 0 (#)
83
84 ; Digital PSoC block 02, Communications Type B
85 0000 DCB02DR0: equ 28h ; data register 0 (#)
86 0000 DCB02DR1: equ 29h ; data register 1 (W)
87 0000 DCB02DR2: equ 2Ah ; data register 2 (RW)
88 0000 DCB02CR0: equ 2Bh ; control & status register 0 (#)
89
90 ; Digital PSoC block 03, Communications Type B
91 0000 DCB03DR0: equ 2Ch ; data register 0 (#)
92 0000 DCB03DR1: equ 2Dh ; data register 1 (W)
93 0000 DCB03DR2: equ 2Eh ; data register 2 (RW)
94 0000 DCB03CR0: equ 2Fh ; control & status register 0 (#)
95
96 ;-------------------------------------
97 ; Analog Resource Control Registers
98 ;-------------------------------------
99 0000 AMX_IN: equ 60h ; Analog Input Multiplexor Control (RW)
100 0000 AMX_IN_ACI1: equ 0Ch ; MASK: column 1 input mux
101 0000 AMX_IN_ACI0: equ 03h ; MASK: column 0 input mux
102
103 0000 ARF_CR: equ 63h ; Analog Reference Control Register (RW)
104 0000 ARF_CR_HBE: equ 40h ; MASK: Bias level control
105 0000 ARF_CR_REF: equ 38h ; MASK: Analog Reference controls
106 0000 ARF_CR_REFPWR: equ 07h ; MASK: Analog Reference power
107 0000 ARF_CR_APWR: equ 04h ; MASK: use deprecated; see datasheet
108 0000 ARF_CR_SCPWR: equ 03h ; MASK: Switched Cap block power
109
110 0000 CMP_CR0: equ 64h ; Analog Comparator Bus 0 Register (#)
111 0000 CMP_CR0_COMP1: equ 20h ; MASK: Column 1 comparator state (R)
112 0000 CMP_CR0_COMP0: equ 10h ; MASK: Column 0 comparator state (R)
113 0000 CMP_CR0_AINT1: equ 02h ; MASK: Column 1 interrupt source (RW)
114 0000 CMP_CR0_AINT0: equ 01h ; MASK: Column 0 interrupt source (RW)
115
116 0000 ASY_CR: equ 65h ; Analog Synchronizaton Control (#)
117 0000 ASY_CR_SARCOUNT: equ 70h ; MASK: SAR support: resolution count (W)
118 0000 ASY_CR_SARSIGN: equ 08h ; MASK: SAR support: sign (RW)
119 0000 ASY_CR_SARCOL: equ 06h ; MASK: SAR support: column spec (RW)
120 0000 ASY_CR_SYNCEN: equ 01h ; MASK: Stall bit (RW)
121
122 0000 CMP_CR1: equ 66h ; Analog Comparator Bus 1 Register (RW)
123 0000 CMP_CR1_ASYNCH1: equ 20h ; MASK: Column 1 comparator bus synch
124 0000 CMP_CR1_ASYNCH0: equ 10h ; MASK: Column 0 comparator bus synch
125
126 ;---------------------------------------------------
127 ; Analog PSoC block Registers
128 ;
129 ; Note: the following registers are mapped into
130 ; both register bank 0 AND register bank 1.
131 ;---------------------------------------------------
132
133 ; Continuous Time PSoC block Type B Row 0 Col 0
134 0000 ACB00CR3: equ 70h ; Control register 3 (RW)
135 0000 ACB00CR0: equ 71h ; Control register 0 (RW)
136 0000 ACB00CR1: equ 72h ; Control register 1 (RW)
137 0000 ACB00CR2: equ 73h ; Control register 2 (RW)
138
139 ; Continuous Time PSoC block Type B Row 0 Col 1
140 0000 ACB01CR3: equ 74h ; Control register 3 (RW)
141 0000 ACB01CR0: equ 75h ; Control register 0 (RW)
142 0000 ACB01CR1: equ 76h ; Control register 1 (RW)
143 0000 ACB01CR2: equ 77h ; Control register 2 (RW)
144
145 ; Switched Cap PSoC blockType C Row 1 Col 0
146 0000 ASC10CR0: equ 80h ; Control register 0 (RW)
147 0000 ASC10CR1: equ 81h ; Control register 1 (RW)
148 0000 ASC10CR2: equ 82h ; Control register 2 (RW)
149 0000 ASC10CR3: equ 83h ; Control register 3 (RW)
150
151 ; Switched Cap PSoC blockType D Row 1 Col 1
152 0000 ASD11CR0: equ 84h ; Control register 0 (RW)
153 0000 ASD11CR1: equ 85h ; Control register 1 (RW)
154 0000 ASD11CR2: equ 86h ; Control register 2 (RW)
155 0000 ASD11CR3: equ 87h ; Control register 3 (RW)
156
157 ; Switched Cap PSoC blockType D Row 2 Col 0
158 0000 ASD20CR0: equ 90h ; Control register 0 (RW)
159 0000 ASD20CR1: equ 91h ; Control register 1 (RW)
160 0000 ASD20CR2: equ 92h ; Control register 2 (RW)
161 0000 ASD20CR3: equ 93h ; Control register 3 (RW)
162
163 ; Switched Cap PSoC blockType C Row 2 Col 1
164 0000 ASC21CR0: equ 94h ; Control register 0 (RW)
165 0000 ASC21CR1: equ 95h ; Control register 1 (RW)
166 0000 ASC21CR2: equ 96h ; Control register 2 (RW)
167 0000 ASC21CR3: equ 97h ; Control register 3 (RW)
168
169 ;------------------------------------------------
170 ; Row Digital Interconnects
171 ;
172 ; Note: the following registers are mapped into
173 ; both register bank 0 AND register bank 1.
174 ;------------------------------------------------
175
176 0000 RDI0RI: equ B0h ; Row Digital Interconnect Row 0 Input Reg (RW)
177 0000 RDI0SYN: equ B1h ; Row Digital Interconnect Row 0 Sync Reg (RW)
178 0000 RDI0IS: equ B2h ; Row 0 Input Select Register (RW)
179 0000 RDI0LT0: equ B3h ; Row 0 Look Up Table Register 0 (RW)
180 0000 RDI0LT1: equ B4h ; Row 0 Look Up Table Register 1 (RW)
181 0000 RDI0RO0: equ B5h ; Row 0 Output Register 0 (RW)
182 0000 RDI0RO1: equ B6h ; Row 0 Output Register 1 (RW)
183
184 ;------------------------------------------------
185 ; I2C Configuration Registers
186 ;------------------------------------------------
187 0000 I2C_CFG: equ D6h ; I2C Configuration Register (RW)
188 0000 I2C_CFG_PINSEL: equ 40h ; MASK: Select P1[0] and P1[1] for I2C
189 0000 I2C_CFG_BUSERR_IE: equ 20h ; MASK: Enable interrupt on Bus Error
190 0000 I2C_CFG_STOP_IE: equ 10h ; MASK: Enable interrupt on Stop
191 0000 I2C_CFG_CLK_RATE_100K: equ 00h ; MASK: I2C clock set at 100K
192 0000 I2C_CFG_CLK_RATE_400K: equ 04h ; MASK: I2C clock set at 400K
193 0000 I2C_CFG_CLK_RATE_50K: equ 08h ; MASK: I2C clock set at 50K
194 0000 I2C_CFG_CLK_RATE_1M6: equ 0Ch ; MASK: I2C clock set at 1.6M
195 0000 I2C_CFG_CLK_RATE: equ 0Ch ; MASK: I2C clock rate setting mask
196 0000 I2C_CFG_PSELECT_MASTER: equ 02h ; MASK: Enable I2C Master
197 0000 I2C_CFG_PSELECT_SLAVE: equ 01h ; MASK: Enable I2C Slave
198
199 0000 I2C_SCR: equ D7h ; I2C Status and Control Register (#)
200 0000 I2C_SCR_BUSERR: equ 80h ; MASK: I2C Bus Error detected (RC)
201 0000 I2C_SCR_LOSTARB: equ 40h ; MASK: I2C Arbitration lost (RC⌨️ 快捷键说明
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