📄 pga.lst
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99 0000 AMX_IN: equ 60h ; Analog Input Multiplexor Control (RW)
100 0000 AMX_IN_ACI1: equ 0Ch ; MASK: column 1 input mux
101 0000 AMX_IN_ACI0: equ 03h ; MASK: column 0 input mux
102
103 0000 ARF_CR: equ 63h ; Analog Reference Control Register (RW)
104 0000 ARF_CR_HBE: equ 40h ; MASK: Bias level control
105 0000 ARF_CR_REF: equ 38h ; MASK: Analog Reference controls
106 0000 ARF_CR_REFPWR: equ 07h ; MASK: Analog Reference power
107 0000 ARF_CR_APWR: equ 04h ; MASK: use deprecated; see datasheet
108 0000 ARF_CR_SCPWR: equ 03h ; MASK: Switched Cap block power
109
110 0000 CMP_CR0: equ 64h ; Analog Comparator Bus 0 Register (#)
111 0000 CMP_CR0_COMP1: equ 20h ; MASK: Column 1 comparator state (R)
112 0000 CMP_CR0_COMP0: equ 10h ; MASK: Column 0 comparator state (R)
113 0000 CMP_CR0_AINT1: equ 02h ; MASK: Column 1 interrupt source (RW)
114 0000 CMP_CR0_AINT0: equ 01h ; MASK: Column 0 interrupt source (RW)
115
116 0000 ASY_CR: equ 65h ; Analog Synchronizaton Control (#)
117 0000 ASY_CR_SARCOUNT: equ 70h ; MASK: SAR support: resolution count (W)
118 0000 ASY_CR_SARSIGN: equ 08h ; MASK: SAR support: sign (RW)
119 0000 ASY_CR_SARCOL: equ 06h ; MASK: SAR support: column spec (RW)
120 0000 ASY_CR_SYNCEN: equ 01h ; MASK: Stall bit (RW)
121
122 0000 CMP_CR1: equ 66h ; Analog Comparator Bus 1 Register (RW)
123 0000 CMP_CR1_ASYNCH1: equ 20h ; MASK: Column 1 comparator bus synch
124 0000 CMP_CR1_ASYNCH0: equ 10h ; MASK: Column 0 comparator bus synch
125
126 ;---------------------------------------------------
127 ; Analog PSoC block Registers
128 ;
129 ; Note: the following registers are mapped into
130 ; both register bank 0 AND register bank 1.
131 ;---------------------------------------------------
132
133 ; Continuous Time PSoC block Type B Row 0 Col 0
134 0000 ACB00CR3: equ 70h ; Control register 3 (RW)
135 0000 ACB00CR0: equ 71h ; Control register 0 (RW)
136 0000 ACB00CR1: equ 72h ; Control register 1 (RW)
137 0000 ACB00CR2: equ 73h ; Control register 2 (RW)
138
139 ; Continuous Time PSoC block Type B Row 0 Col 1
140 0000 ACB01CR3: equ 74h ; Control register 3 (RW)
141 0000 ACB01CR0: equ 75h ; Control register 0 (RW)
142 0000 ACB01CR1: equ 76h ; Control register 1 (RW)
143 0000 ACB01CR2: equ 77h ; Control register 2 (RW)
144
145 ; Switched Cap PSoC blockType C Row 1 Col 0
146 0000 ASC10CR0: equ 80h ; Control register 0 (RW)
147 0000 ASC10CR1: equ 81h ; Control register 1 (RW)
148 0000 ASC10CR2: equ 82h ; Control register 2 (RW)
149 0000 ASC10CR3: equ 83h ; Control register 3 (RW)
150
151 ; Switched Cap PSoC blockType D Row 1 Col 1
152 0000 ASD11CR0: equ 84h ; Control register 0 (RW)
153 0000 ASD11CR1: equ 85h ; Control register 1 (RW)
154 0000 ASD11CR2: equ 86h ; Control register 2 (RW)
155 0000 ASD11CR3: equ 87h ; Control register 3 (RW)
156
157 ; Switched Cap PSoC blockType D Row 2 Col 0
158 0000 ASD20CR0: equ 90h ; Control register 0 (RW)
159 0000 ASD20CR1: equ 91h ; Control register 1 (RW)
160 0000 ASD20CR2: equ 92h ; Control register 2 (RW)
161 0000 ASD20CR3: equ 93h ; Control register 3 (RW)
162
163 ; Switched Cap PSoC blockType C Row 2 Col 1
164 0000 ASC21CR0: equ 94h ; Control register 0 (RW)
165 0000 ASC21CR1: equ 95h ; Control register 1 (RW)
166 0000 ASC21CR2: equ 96h ; Control register 2 (RW)
167 0000 ASC21CR3: equ 97h ; Control register 3 (RW)
168
169 ;------------------------------------------------
170 ; Row Digital Interconnects
171 ;
172 ; Note: the following registers are mapped into
173 ; both register bank 0 AND register bank 1.
174 ;------------------------------------------------
175
176 0000 RDI0RI: equ B0h ; Row Digital Interconnect Row 0 Input Reg (RW)
177 0000 RDI0SYN: equ B1h ; Row Digital Interconnect Row 0 Sync Reg (RW)
178 0000 RDI0IS: equ B2h ; Row 0 Input Select Register (RW)
179 0000 RDI0LT0: equ B3h ; Row 0 Look Up Table Register 0 (RW)
180 0000 RDI0LT1: equ B4h ; Row 0 Look Up Table Register 1 (RW)
181 0000 RDI0RO0: equ B5h ; Row 0 Output Register 0 (RW)
182 0000 RDI0RO1: equ B6h ; Row 0 Output Register 1 (RW)
183
184 ;------------------------------------------------
185 ; I2C Configuration Registers
186 ;------------------------------------------------
187 0000 I2C_CFG: equ D6h ; I2C Configuration Register (RW)
188 0000 I2C_CFG_PINSEL: equ 40h ; MASK: Select P1[0] and P1[1] for I2C
189 0000 I2C_CFG_BUSERR_IE: equ 20h ; MASK: Enable interrupt on Bus Error
190 0000 I2C_CFG_STOP_IE: equ 10h ; MASK: Enable interrupt on Stop
191 0000 I2C_CFG_CLK_RATE_100K: equ 00h ; MASK: I2C clock set at 100K
192 0000 I2C_CFG_CLK_RATE_400K: equ 04h ; MASK: I2C clock set at 400K
193 0000 I2C_CFG_CLK_RATE_50K: equ 08h ; MASK: I2C clock set at 50K
194 0000 I2C_CFG_CLK_RATE_1M6: equ 0Ch ; MASK: I2C clock set at 1.6M
195 0000 I2C_CFG_CLK_RATE: equ 0Ch ; MASK: I2C clock rate setting mask
196 0000 I2C_CFG_PSELECT_MASTER: equ 02h ; MASK: Enable I2C Master
197 0000 I2C_CFG_PSELECT_SLAVE: equ 01h ; MASK: Enable I2C Slave
198
199 0000 I2C_SCR: equ D7h ; I2C Status and Control Register (#)
200 0000 I2C_SCR_BUSERR: equ 80h ; MASK: I2C Bus Error detected (RC)
201 0000 I2C_SCR_LOSTARB: equ 40h ; MASK: I2C Arbitration lost (RC)
202 0000 I2C_SCR_STOP: equ 20h ; MASK: I2C Stop detected (RC)
203 0000 I2C_SCR_ACK: equ 10h ; MASK: ACK the last byte (RW)
204 0000 I2C_SCR_ADDR: equ 08h ; MASK: Address rcv'd is Slave address (RC)
205 0000 I2C_SCR_XMIT: equ 04h ; MASK: Set transfer to tranmit mode (RW)
206 0000 I2C_SCR_LRB: equ 02h ; MASK: Last recieved bit (RC)
207 0000 I2C_SCR_BYTECOMPLETE: equ 01h ; MASK: Transfer of byte complete (RC)
208
209 0000 I2C_DR: equ D8h ; I2C Data Register (RW)
210
211 0000 I2C_MSCR: equ D9h ; I2C Master Status and Control Register (#)
212 0000 I2C_MSCR_BUSY: equ 08h ; MASK: I2C Busy (Start detected) (R)
213 0000 I2C_MSCR_MODE: equ 04h ; MASK: Start has been generated (R)
214 0000 I2C_MSCR_RESTART: equ 02h ; MASK: Generate a Restart condition (RW)
215 0000 I2C_MSCR_START: equ 01h ; MASK: Generate a Start condition (RW)
216
217 ;------------------------------------------------
218 ; System and Global Resource Registers
219 ;------------------------------------------------
220 0000 INT_CLR0: equ DAh ; Interrupt Clear Register 0 (RW)
221 ; Use INT_MSK0 bit field masks
222 0000 INT_CLR1: equ DBh ; Interrupt Clear Register 1 (RW)
223 ; Use INT_MSK1 bit field masks
224 0000 INT_CLR3: equ DDh ; Interrupt Clear Register 3 (RW)
225 ; Use INT_MSK3 bit field masks
226
227 0000 INT_MSK3: equ DEh ; I2C and Software Mask Register (RW)
228 0000 INT_MSK3_ENSWINT: equ 80h ; MASK: enable/disable SW interrupt
229 0000 INT_MSK3_I2C: equ 01h ; MASK: enable/disable I2C interrupt
230
231 0000 INT_MSK0: equ E0h ; General Interrupt Mask Register (RW)
232 0000 INT_MSK0_VC3: equ 80h ; MASK: enable/disable VC3 interrupt
233 0000 INT_MSK0_SLEEP: equ 40h ; MASK: enable/disable sleep interrupt
234 0000 INT_MSK0_GPIO: equ 20h ; MASK: enable/disable GPIO interrupt
235 0000 INT_MSK0_ACOLUMN_1: equ 04h ; MASK: enable/disable Analog col 1 interrupt
236 0000 INT_MSK0_ACOLUMN_0: equ 02h ; MASK: enable/disable Analog col 0 interrupt
237 0000 INT_MSK0_VOLTAGE_MONITOR: equ 01h ; MASK: enable/disable Volts interrupt
238
239 0000 INT_MSK1: equ E1h ; Digital PSoC block Mask Register (RW)
240 0000 INT_MSK1_DCB03: equ 08h ; MASK: enable/disable DCB03 block interrupt
241 0000 INT_MSK1_DCB02: equ 04h ; MASK: enable/disable DCB02 block interrupt
242 0000 INT_MSK1_DBB01: equ 02h ; MASK: enable/disable DBB01 block interrupt
243 0000 INT_MSK1_DBB00: equ 01h ; MASK: enable/disable DBB00 block interrupt
244
245 0000 INT_VC: equ E2h ; Interrupt vector register (RC)
246 0000 RES_WDT: equ E3h ; Watch Dog Timer Register (W)
247
248 ; DECIMATOR Registers
249 0000 DEC_DH: equ E4h ; Data Register (high byte) (RC)
250 0000 DEC_DL: equ E5h ; Data Register ( low byte) (RC)
251 0000 DEC_CR0: equ E6h ; Data Control Register 0 (RW)
252 0000 DEC_CR1: equ E7h ; Data Control Register 1 (RW)
253
254 ; Multiplier and MAC (Multiply/Accumulate) Unit
255 0000 MUL_X: equ E8h ; Multiplier X Register (write) (W)
256 0000 MUL_Y: equ E9h ; Multiplier Y Register (write) (W)
257 0000 MUL_DH: equ EAh ; Multiplier Result Data (high byte read) (R)
258 0000 MUL_DL: equ EBh ; Multiplier Result Data ( low byte read) (R)
259 0000 MAC_X: equ ECh ; write = MAC X register [also see ACC_DR1]
260 0000 ACC_DR1: equ MAC_X ; read = MAC Accumulator, byte 1 (RW)
261 0000 MAC_Y: equ EDh ; write = MAC Y register [also see ACC_DR0]
262 0000 ACC_DR0: equ MAC_Y ; read = MAC Accumulator, byte 0 (RW)
263 0000 MAC_CL0: equ EEh ; write = MAC Clear Accum [also see ACC_DR3]
264 0000 ACC_DR3: equ MAC_CL0 ; read = MAC Accumulator, byte 3 (RW)
265 0000 MAC_CL1: equ EFh ; write = MAC Clear Accum [also see ACC_DR2]
266 0000 ACC_DR2: equ MAC_CL1 ; read = MAC Accumulator, byte 2 (RW)
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