📄 pga.lst
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HI-TECH Software Macro Assembler (PSoC MCU) V9.60PL1
Mon Nov 26 12:52:32 2007
1 ;;*****************************************************************************
2 ;;*****************************************************************************
3 ;; FILENAME: PGA.inc ( PGA )
4 ;; Version: 3.2, Updated on 2006/01/14 at 16:06:54
5 ;; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
6 ;;
7 ;; DESCRIPTION: Assembler declarations for the PGA user module interface for
8 ;; the 22/24/27/29xxx PSoC family of devices.
9 ;;-----------------------------------------------------------------------------
10 ;; Copyright (c) Cypress MicroSystems 2001-2004. All Rights Reserved.
11 ;;*****************************************************************************
12 ;;*****************************************************************************
13
14 ;--------------------------------------------------
15 ; Constants for PGA API's.
16 ;--------------------------------------------------
17
18 0000 PGA_OFF: equ 0
19 0000 PGA_LOWPOWER: equ 1
20 0000 PGA_MEDPOWER: equ 2
21 0000 PGA_HIGHPOWER: equ 3
22
23 0000 PGA_G48_0: equ 0Ch
24 0000 PGA_G24_0: equ 1Ch
25 0000 PGA_G16_0: equ 08h
26 0000 PGA_G8_00: equ 18h
27 0000 PGA_G5_33: equ 28h
28 0000 PGA_G4_00: equ 38h
29 0000 PGA_G3_20: equ 48h
30 0000 PGA_G2_67: equ 58h
31 0000 PGA_G2_27: equ 68h
32 0000 PGA_G2_00: equ 78h
33 0000 PGA_G1_78: equ 88h
34 0000 PGA_G1_60: equ 98h
35 0000 PGA_G1_46: equ A8h
36 0000 PGA_G1_33: equ B8h
37 0000 PGA_G1_23: equ C8h
38 0000 PGA_G1_14: equ D8h
39 0000 PGA_G1_06: equ E8h
40 0000 PGA_G1_00: equ F8h
41 0000 PGA_G0_93: equ E0h
42 0000 PGA_G0_87: equ D0h
43 0000 PGA_G0_81: equ C0h
44 0000 PGA_G0_75: equ B0h
45 0000 PGA_G0_68: equ A0h
46 0000 PGA_G0_62: equ 90h
47 0000 PGA_G0_56: equ 80h
48 0000 PGA_G0_50: equ 70h
49 0000 PGA_G0_43: equ 60h
50 0000 PGA_G0_37: equ 50h
51 0000 PGA_G0_31: equ 40h
52 0000 PGA_G0_25: equ 30h
53 0000 PGA_G0_18: equ 20h
54 0000 PGA_G0_12: equ 10h
55 0000 PGA_G0_06: equ 00h
56
57
58 ;--------------------------------------------------
59 ; Register Address Constants used by PGA
60 ;--------------------------------------------------
61 0000 PGA_GAIN_CR0: equ 75h
62 0000 PGA_GAIN_CR1: equ 76h
63 0000 PGA_GAIN_CR2: equ 77h
64 0000 PGA_GAIN_CR3: equ 74h
1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ;;;
3 ;;; M8C.INC -- M8C24000 Microcontroller Family System Declarations
4 ;;;
5 ;;; Copyright (c) 2003-2004, Cypress MicroSystems, Inc. All rights reserved.
6 ;;;
7 ;;;
8 ;;; This file provides address constants, bit field masks and a set of macro
9 ;;; facilities for the Cypress MicroSystems 24xxx Microcontroller family.
10 ;;;
11 ;;; Last Modified: August 2, 2004
12 ;;;
13 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14
15 ;;=============================================================================
16 ;; Definition of abbreviations used in the descriptions below
17 ;; (RW) The register or bit supports reads and writes
18 ;; (W) The register or bit is write-only
19 ;; (R) The register or bit is read-only
20 ;; (#) Access to the register is bit specific (see the family datasheet)
21 ;; (RC) The register or bit can be read, but writing a 0 will clear it,
22 ;; writing a 1 will have no effect.
23 ;;=============================================================================
24
25 ;;=============================================================================
26 ;; System Registers
27 ;;=============================================================================
28
29 ;----------------------------
30 ; Flag Register Bit Fields
31 ;----------------------------
32 0000 FLAG_XIO_MASK: equ 10h
33 0000 FLAG_SUPER: equ 08h
34 0000 FLAG_CARRY: equ 04h
35 0000 FLAG_ZERO: equ 02h
36 0000 FLAG_GLOBAL_IE: equ 01h
37
38
39 ;;=============================================================================
40 ;; Register Space, Bank 0
41 ;;=============================================================================
42
43 ;------------------------------------------------
44 ; Port Registers
45 ; Note: Also see this address range in Bank 1.
46 ;------------------------------------------------
47 ; Port 0
48 0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
49 0000 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
50 0000 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
51 0000 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
52 ; Port 1
53 0000 PRT1DR: equ 04h ; Port 1 Data Register (RW)
54 0000 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
55 0000 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
56 0000 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
57 ; Port 2
58 0000 PRT2DR: equ 08h ; Port 2 Data Register (RW)
59 0000 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
60 0000 PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
61 0000 PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
62 ; Port 3
63 0000 PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
64 0000 PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
65 0000 PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
66 0000 PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
67
68 ;------------------------------------------------
69 ; Digital PSoC(tm) block Registers
70 ; Note: Also see this address range in Bank 1.
71 ;------------------------------------------------
72 ; Digital PSoC block 00, Basic Type B
73 0000 DBB00DR0: equ 20h ; data register 0 (#)
74 0000 DBB00DR1: equ 21h ; data register 1 (W)
75 0000 DBB00DR2: equ 22h ; data register 2 (RW)
76 0000 DBB00CR0: equ 23h ; control & status register 0 (#)
77
78 ; Digital PSoC block 01, Basic Type B
79 0000 DBB01DR0: equ 24h ; data register 0 (#)
80 0000 DBB01DR1: equ 25h ; data register 1 (W)
81 0000 DBB01DR2: equ 26h ; data register 2 (RW)
82 0000 DBB01CR0: equ 27h ; control & status register 0 (#)
83
84 ; Digital PSoC block 02, Communications Type B
85 0000 DCB02DR0: equ 28h ; data register 0 (#)
86 0000 DCB02DR1: equ 29h ; data register 1 (W)
87 0000 DCB02DR2: equ 2Ah ; data register 2 (RW)
88 0000 DCB02CR0: equ 2Bh ; control & status register 0 (#)
89
90 ; Digital PSoC block 03, Communications Type B
91 0000 DCB03DR0: equ 2Ch ; data register 0 (#)
92 0000 DCB03DR1: equ 2Dh ; data register 1 (W)
93 0000 DCB03DR2: equ 2Eh ; data register 2 (RW)
94 0000 DCB03CR0: equ 2Fh ; control & status register 0 (#)
95
96 ;-------------------------------------
97 ; Analog Resource Control Registers
98 ;-------------------------------------
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