📄 psocconfig.lis
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0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
0000 SYSTEM_STACK_PAGE: equ 0
0000 SYSTEM_STACK_BASE_ADDR: equ 0h
0000 SYSTEM_LARGE_MEMORY_MODEL: equ 0
0001 SYSTEM_SMALL_MEMORY_MODEL: equ 1
0001 IMAGECRAFT: equ 1
0002 HITECH: equ 2
0001 TOOLCHAIN: equ IMAGECRAFT
0001 SYSTEM_TOOLS: equ 1
0001 SYSTEM_IDXPG_TRACKS_STK_PP: equ 1
0000 SYSTEM_IDXPG_TRACKS_IDX_PP: equ 0
0000 SYSTEM_MULTIPAGE_STACK: equ 0
0000
0000
0000 ; ******* Function Class Definitions *******
0000 ;
0000 ; These definitions are used to describe RAM access patterns. They provide
0000 ; documentation and they control prologue and epilogue macros that perform
0000 ; the necessary housekeeping functions for a large memory model device like
0000 ; the CY8C29x66.
0000
0001 RAM_USE_CLASS_1: equ 1 ; PUSH, POP & I/O access
0002 RAM_USE_CLASS_2: equ 2 ; Indexed address mode on stack page
0004 RAM_USE_CLASS_3: equ 4 ; Indexed address mode to any page
0008 RAM_USE_CLASS_4: equ 8 ; Direct/Indirect address mode access
0000
0000
0000 ; ******* Page Pointer Manipulation Macros *******
0000 ;
0000 ; Most of the following macros are conditionally compiled so they only
0000 ; produce code if the large memory model is selected.
0000
0000 ;-----------------------------------------------
0000 ; Set Stack Page Macro
0000 ;-----------------------------------------------
0000 ;
0000 ; DESC: Modify STK_PP in the large or small memory Models.
0000 ;
0000 ; INPUT: Constant (e.g., SYSTEM_STACK_PAGE) that specifies the RAM page on
0000 ; which stack operations like PUSH and POP store and retrieve their
0000 ; data
0000 ;
0000 ; COST: 8 instruction cycles (in LMM only)
0000
0000 macro RAM_SETPAGE_STK( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[STK_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_CUR( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[CUR_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_IDX( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[IDX_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_MVR( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[MVR_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_MVW( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[MVW_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_IDX2STK
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 IF ( SYSTEM_MULTIPAGE_STACK )
0000 mov A, reg[STK_PP]
0000 mov reg[IDX_PP], A
0000 ELSE
0000 RAM_SETPAGE_IDX SYSTEM_STACK_PAGE
0000 ENDIF
0000 ENDIF
0000 macro RAM_CHANGE_PAGE_MODE( MODE )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
0000 or F, FLAG_PGMODE_MASK & @MODE
0000 ENDIF
0000 macro RAM_SET_NATIVE_PAGING
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
0000 or F, FLAG_PGMODE_11b ; LMM w/ IndexPage<==>StackPage
0000 ENDIF ; PGMODE LOCKED
0000 IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
0000 or F, FLAG_PGMODE_10b ; LMM with independent IndexPage
0000 ENDIF ; PGMODE FREE
0000 ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
0000 macro RAM_RESTORE_NATIVE_PAGING
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
0000 RAM_CHANGE_PAGE_MODE FLAG_PGMODE_11b ; LMM w/ IndexPage<==>StackPage
0000 ENDIF ; PGMODE LOCKED
0000 IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
0000 RAM_CHANGE_PAGE_MODE FLAG_PGMODE_10b ; LMM with independent IndexPage
0000 ENDIF ; PGMODE FREE
0000 ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
0000 macro RAM_X_POINTS_TO_STACKPAGE
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 or F, FLAG_PGMODE_01b
0000 ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
0000 macro RAM_X_POINTS_TO_INDEXPAGE
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 and F, ~FLAG_PGMODE_01b
0000 ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
0000 macro RAM_PROLOGUE( ACTUAL_CLASS )
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_1 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_1
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_2 )
0000 IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
0000 RAM_X_POINTS_TO_STACKPAGE ; exit native paging mode!
0000 ENDIF
0000 ENDIF ; RAM_USE_CLASS_2
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_3 )
0000 IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
0000 RAM_X_POINTS_TO_INDEXPAGE ; exit native paging mode!
0000 ENDIF
0000 ENDIF ; RAM_USE_CLASS_3
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_4 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_4
0000
0000 macro RAM_EPILOGUE( ACTUAL_CLASS )
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_1 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_1
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_2 )
0000 RAM_RESTORE_NATIVE_PAGING
0000 ENDIF ; RAM_USE_CLASS_2
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_3 )
0000 RAM_RESTORE_NATIVE_PAGING
0000 ENDIF ; RAM_USE_CLASS_3
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_4 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_4
0000
0000 macro REG_PRESERVE( IOReg )
0000 mov A, reg[ @IOReg ]
0000 push A
0000 macro REG_RESTORE( IOReg )
0000 pop A
0000 mov reg[ @IOReg ], A
0000 macro ISR_PRESERVE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_PRESERVE CUR_PP
0000 REG_PRESERVE IDX_PP
0000 REG_PRESERVE MVR_PP
0000 REG_PRESERVE MVW_PP
0000 ENDIF
0000 macro ISR_RESTORE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_RESTORE MVW_PP
0000 REG_RESTORE MVR_PP
0000 REG_RESTORE IDX_PP
0000 REG_RESTORE CUR_PP
0000 ENDIF
0000 CPU_CLOCK: equ 0h ;CPU clock value
0007 CPU_CLOCK_MASK: equ 7h ;CPU clock mask
0000 CPU_CLOCK_JUST: equ 0h ;CPU clock value justified
0000 SELECT_32K: equ 0h ;32K select value
0080 SELECT_32K_MASK: equ 80h ;32K select mask
0000 SELECT_32K_JUST: equ 0h ;32K select value justified
0000 PLL_MODE: equ 0h ;PLL mode value
0040 PLL_MODE_MASK: equ 40h ;PLL mode mask
0000 PLL_MODE_JUST: equ 0h ;PLL mode value justified
0000 SLEEP_TIMER: equ 0h ;Sleep Timer value
0018 SLEEP_TIMER_MASK: equ 18h ;Sleep Timer mask
0000 SLEEP_TIMER_JUST: equ 0h ;Sleep Timer value justified
0000 LVD_TBEN: equ 0 ; Low Voltage Throttle-back enable value
0008 LVD_TBEN_MASK: equ 8 ; Low Voltage Throttle-back enable mask
0000 LVD_TBEN_JUST: equ 0 ; Low Voltage Throttle-back enable justified
0007 TRIP_VOLTAGE: equ 7h ;Trip Voltage value
0007 TRIP_VOLTAGE_MASK: equ 7h ;Trip Voltage mask
0007 TRIP_VOLTAGE_JUST: equ 7h ;Trip Voltage justified
0000
0010 POWER_SETTING: equ 10h
0010 POWER_SET_5V0: equ 10h ; MASK for 5.0V operation, fast and slow
0010 POWER_SET_5V0_24MHZ: equ 10h ; Power Setting value for 5.0V fast
0011 POWER_SET_5V0_6MHZ: equ 11h ; Power Setting value for 5.0V slow
0008 POWER_SET_3V3: equ 08h ; MASK for 3.3V operation, fast and slow
0008 POWER_SET_3V3_24MHZ: equ 08h ; Power Setting value for 3.3V fast
0009 POWER_SET_3V3_6MHZ: equ 09h ; Power Setting value for 3.3V slow
0006 POWER_SET_2V7: equ 06h ; MASK for 2.7V operation, fast and slow
0004 POWER_SET_2V7_12MHZ: equ 04h ; MASK for 2.7V, 12MHZ operation
0002 POWER_SET_2V7_6MHZ: equ 02h ; MASK for 2.7V, 6MHZ operation
0001 POWER_SET_SLOW_IMO: equ 01h ; MASK for slow Internal Main Oscillator (IMO)
0000
0000 COMM_RX_PRESENT: equ 0 ;1 = TRUE
0000 WATCHDOG_ENABLE: equ 0 ;Watchdog Enable 1 = Enable
0000
0000 CLOCK_DIV_VC1: equ 0h ;VC1 clock divider
00F0 CLOCK_DIV_VC1_MASK: equ f0h ;VC1 clock divider mask
0000 CLOCK_DIV_VC1_JUST: equ 0h ;VC1 clock divider justified
0000 CLOCK_DIV_VC2: equ 0h ;VC2 clock divider
000F CLOCK_DIV_VC2_MASK: equ fh ;VC2 clock divider mask
0000 CLOCK_DIV_VC2_JUST: equ 0h ;VC2 clock divider justified
0000 CLOCK_INPUT_VC3: equ 0h ;VC3 clock source
0003 CLOCK_INPUT_VC3_MASK: equ 3h ;VC3 clock source mask
0000 CLOCK_INPUT_VC3_JUST: equ 0h ;VC3 clock source justified
0000 CLOCK_DIV_VC3: equ 0h ;VC3 clock divider
00FF CLOCK_DIV_VC3_MASK: equ ffh ;VC3 clock divider mask
0000 CLOCK_DIV_VC3_JUST: equ 0h ;VC3 clock divider justified
0000 ANALOG_BUFFER_PWR: equ 0h ;Analog buffer power level
0001 ANALOG_BUFFER_PWR_MASK: equ 1h ;Analog buffer power level mask
0000 ANALOG_BUFFER_PWR_JUST: equ 0h ;Analog buffer power level justified
0005 ANALOG_POWER: equ 5h ;Analog power control
0007 ANALOG_POWER_MASK: equ 7h ;Analog power control mask
0005 ANALOG_POWER_JUST: equ 5h ;Analog power control justified
0000 OP_AMP_BIAS: equ 0h ;Op amp bias level
0040 OP_AMP_BIAS_MASK: equ 40h ;Op amp bias level mask
0000 OP_AMP_BIAS_JUST: equ 0h ;Op amp bias level justified
0000 REF_MUX: equ 0h ;Ref mux setting
0038 REF_MUX_MASK: equ 38h ;Ref mux setting mask
0000 REF_MUX_JUST: equ 0h ;Ref mux setting justified
0000 AGND_BYPASS: equ 0h ;AGndBypass setting
0040 AGND_BYPASS_MASK: equ 40h ;AGndBypass setting mask
0000 AGND_BYPASS_JUST: equ 0h ;AGndBypass setting justified
0000 SYSCLK_SOURCE: equ (0h | 0h) ;SysClk Source setting
0006 SYSCLK_SOURCE_MASK: equ (4h | 2h) ;SysClk Source setting mask
0000 SYSCLK_SOURCE_JUST: equ (0h | 0h) ;SysClk Source setting justified
0000 SYSCLK_2_DISABLE: equ 0h ;SysClk*2 Disable setting
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