📄 psocgpioint.lst
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502 ;
503 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
504 ; M8C_EnableIntMask INT_MSKN, MASK
505 ;
506 ; where INT_MSKN is INT_MSK0, INT_MSK1 or INT_MSK3
507 ; and MASK is the bit set to enable or disable
508 ;----------------------------------------------------
509 ; Disable Interrupt Bit Mask(s)
510 macro M8C_DisableIntMask
511 and reg[@0], ~@1 ; disable specified interrupt enable bit
512 0000' endm
513
514 ; Enable Interrupt Bit Mask(s)
515 macro M8C_EnableIntMask
516 or reg[@0], @1 ; enable specified interrupt enable bit
517 0000' endm
518
519 ;----------------------------------------------------
520 ; Clear Posted Interrupt Flag Mask
521 ;
522 ; Use the following macros to clear the
523 ; bits in the Interrupt Clear registers,
524 ; INT_CLR0, INT_CLR1 or INT_CLR3.
525 ; Usage: M8C_ClearIntFlag INT_CLRN, MASK
526 ;
527 ; where INT_MSKN is INT_CLR0, INT_CLR1 or INT_CLR3
528 ; and MASK is the bit set to enable or disable
529 ;----------------------------------------------------
530 macro M8C_ClearIntFlag
531 mov reg[@0], ~@1 ; clear specified interrupt enable bit
532 0000' endm
533
534 ;----------------------------------------------------
535 ; Power-On Reset & WatchDog Timer Functions
536 ;----------------------------------------------------
537 macro M8C_EnableWatchDog
538 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
539 0000' endm
540
541 macro M8C_ClearWDT
542 mov reg[RES_WDT], 00h
543 0000' endm
544
545 macro M8C_ClearWDTAndSleep
546 mov reg[RES_WDT], 38h
547 0000' endm
548
549 ;----------------------------------------------------
550 ; CPU Stall for Analog PSoC Block Writes
551 ;----------------------------------------------------
552 macro M8C_Stall
553 or reg[ASY_CR], ASY_CR_SYNCEN
554 0000' endm
555
556 macro M8C_Unstall
557 and reg[ASY_CR], ~ASY_CR_SYNCEN
558 0000' endm
559
560 ;----------------------------------------------------
561 ; Sleep, CPU Stop & Software Reset
562 ;----------------------------------------------------
563 macro M8C_Sleep
564 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
565 ; The next instruction to be executed depends on the state of the
566 ; various interrupt enable bits. If some interrupts are enabled
567 ; and the global interrupts are disabled, the next instruction will
568 ; be the one that follows the invocation of this macro. If global
569 ; interrupts are also enabled then the next instruction will be
570 ; from the interrupt vector table. If no interrupts are enabled
571 ; then the CPU sleeps forever.
572 0000' endm
573
574 macro M8C_Stop
575 ; In general, you probably don't want to do this, but here's how:
576 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
577 ; Next instruction to be executed is located in the interrupt
578 ; vector table entry for Power-On Reset.
579 0000' endm
580
581 macro M8C_Reset
582 ; Restore CPU to the power-on reset state.
583 mov A, 0
584 SSC
585 ; Next non-supervisor instruction will be at interrupt vector 0.
586 0000' endm
587
588 ;----------------------------------------------------
589 ; ImageCraft Code Compressor Actions
590 ;----------------------------------------------------
591 ; Suspend Code Compressor
592 ; Must not span a RET or RETI instruction
593 ; without resuming code compression
594 macro Suspend_CodeCompressor
595 or F, 0
596 0000' endm
597
598 ; Resume Code Compression
599 macro Resume_CodeCompressor
600 add SP, 0
601 0000' endm
1 ; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
2 ;
3 ;
4 ; PSoCGPIOINT.inc
5 ;
6 ; Data: 29 October, 2001
7 ; Copyright Cypress MicroSystems 2001
8 ;
9 ; This file is generated by the Device Editor on Application Generation.
10 ; It contains equates that are useful in writing code relating to GPIO
11 ; related interrupts.
12 ;
13 ; DO NOT EDIT THIS FILE MANUALLY, AS IT IS OVERWRITTEN!!!
14 ; Edits to this file will not be preserved.
15 ;
16 ; HALL_2 address and mask equates
17 0000 HALL_2_Data_ADDR: equ 8h
18 0000 HALL_2_DriveMode_0_ADDR: equ 108h
19 0000 HALL_2_DriveMode_1_ADDR: equ 109h
20 0000 HALL_2_DriveMode_2_ADDR: equ bh
21 0000 HALL_2_GlobalSelect_ADDR: equ ah
22 0000 HALL_2_IntCtrl_0_ADDR: equ 10ah
23 0000 HALL_2_IntCtrl_1_ADDR: equ 10bh
24 0000 HALL_2_IntEn_ADDR: equ 9h
25 0000 HALL_2_MASK: equ 2h
26 ; HALL_1 address and mask equates
27 0000 HALL_1_Data_ADDR: equ 8h
28 0000 HALL_1_DriveMode_0_ADDR: equ 108h
29 0000 HALL_1_DriveMode_1_ADDR: equ 109h
30 0000 HALL_1_DriveMode_2_ADDR: equ bh
31 0000 HALL_1_GlobalSelect_ADDR: equ ah
32 0000 HALL_1_IntCtrl_0_ADDR: equ 10ah
33 0000 HALL_1_IntCtrl_1_ADDR: equ 10bh
34 0000 HALL_1_IntEn_ADDR: equ 9h
35 0000 HALL_1_MASK: equ 1h
36 ; HALL_3 address and mask equates
37 0000 HALL_3_Data_ADDR: equ 8h
38 0000 HALL_3_DriveMode_0_ADDR: equ 108h
39 0000 HALL_3_DriveMode_1_ADDR: equ 109h
40 0000 HALL_3_DriveMode_2_ADDR: equ bh
41 0000 HALL_3_GlobalSelect_ADDR: equ ah
42 0000 HALL_3_IntCtrl_0_ADDR: equ 10ah
43 0000 HALL_3_IntCtrl_1_ADDR: equ 10bh
44 0000 HALL_3_IntEn_ADDR: equ 9h
45 0000 HALL_3_MASK: equ 4h
46 ; ABS_SEL address and mask equates
47 0000 ABS_SEL_Data_ADDR: equ 0h
48 0000 ABS_SEL_DriveMode_0_ADDR: equ 100h
49 0000 ABS_SEL_DriveMode_1_ADDR: equ 101h
50 0000 ABS_SEL_DriveMode_2_ADDR: equ 3h
51 0000 ABS_SEL_GlobalSelect_ADDR: equ 2h
52 0000 ABS_SEL_IntCtrl_0_ADDR: equ 102h
53 0000 ABS_SEL_IntCtrl_1_ADDR: equ 103h
54 0000 ABS_SEL_IntEn_ADDR: equ 1h
55 0000 ABS_SEL_MASK: equ 1h
56 ; PHASE_SEL address and mask equates
57 0000 PHASE_SEL_Data_ADDR: equ 0h
58 0000 PHASE_SEL_DriveMode_0_ADDR: equ 100h
59 0000 PHASE_SEL_DriveMode_1_ADDR: equ 101h
60 0000 PHASE_SEL_DriveMode_2_ADDR: equ 3h
61 0000 PHASE_SEL_GlobalSelect_ADDR: equ 2h
62 0000 PHASE_SEL_IntCtrl_0_ADDR: equ 102h
63 0000 PHASE_SEL_IntCtrl_1_ADDR: equ 103h
64 0000 PHASE_SEL_IntEn_ADDR: equ 1h
65 0000 PHASE_SEL_MASK: equ 2h
66 ; CRU_SEL address and mask equates
67 0000 CRU_SEL_Data_ADDR: equ 0h
68 0000 CRU_SEL_DriveMode_0_ADDR: equ 100h
69 0000 CRU_SEL_DriveMode_1_ADDR: equ 101h
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