📄 psocconfigtbl.lst
字号:
599 macro Resume_CodeCompressor
600 add SP, 0
601 1DCD endm
1 ; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
2 ;
3 include "m8c.inc"
4 ; Personalization tables
5 export LoadConfigTBL_hitech_tst_Bank1
6 export LoadConfigTBL_hitech_tst_Bank0
7 export LoadConfigTBL_hitech_tst_Ordered
8 AREA lit(rom, rel)
9 06C8 LoadConfigTBL_hitech_tst_Ordered:
10 ; Ordered Global Register values
11 06C8 71 10 M8C_SetBank1
12 06CA 62 00 00 mov reg[00h], 00h ; Port_0_DriveMode_0 register (PRT0DM0)
13 06CD 62 01 FF mov reg[01h], ffh ; Port_0_DriveMode_1 register (PRT0DM1)
14 06D0 70 EF M8C_SetBank0
15 06D2 62 03 F7 mov reg[03h], f7h ; Port_0_DriveMode_2 register (PRT0DM2)
16 06D5 62 02 00 mov reg[02h], 00h ; Port_0_GlobalSelect register (PRT0GS)
17 06D8 71 10 M8C_SetBank1
18 06DA 62 02 00 mov reg[02h], 00h ; Port_0_IntCtrl_0 register (PRT0IC0)
19 06DD 62 03 00 mov reg[03h], 00h ; Port_0_IntCtrl_1 register (PRT0IC1)
20 06E0 70 EF M8C_SetBank0
21 06E2 62 01 00 mov reg[01h], 00h ; Port_0_IntEn register (PRT0IE)
22 06E5 71 10 M8C_SetBank1
23 06E7 62 04 FF mov reg[04h], ffh ; Port_1_DriveMode_0 register (PRT1DM0)
24 06EA 62 05 03 mov reg[05h], 03h ; Port_1_DriveMode_1 register (PRT1DM1)
25 06ED 70 EF M8C_SetBank0
26 06EF 62 07 03 mov reg[07h], 03h ; Port_1_DriveMode_2 register (PRT1DM2)
27 06F2 62 06 00 mov reg[06h], 00h ; Port_1_GlobalSelect register (PRT1GS)
28 06F5 71 10 M8C_SetBank1
29 06F7 62 06 00 mov reg[06h], 00h ; Port_1_IntCtrl_0 register (PRT1IC0)
30 06FA 62 07 00 mov reg[07h], 00h ; Port_1_IntCtrl_1 register (PRT1IC1)
31 06FD 70 EF M8C_SetBank0
32 06FF 62 05 00 mov reg[05h], 00h ; Port_1_IntEn register (PRT1IE)
33 0702 71 10 M8C_SetBank1
34 0704 62 08 F0 mov reg[08h], f0h ; Port_2_DriveMode_0 register (PRT2DM0)
35 0707 62 09 0F mov reg[09h], 0fh ; Port_2_DriveMode_1 register (PRT2DM1)
36 070A 70 EF M8C_SetBank0
37 070C 62 0B 00 mov reg[0bh], 00h ; Port_2_DriveMode_2 register (PRT2DM2)
38 070F 62 0A 00 mov reg[0ah], 00h ; Port_2_GlobalSelect register (PRT2GS)
39 0712 71 10 M8C_SetBank1
40 0714 62 0A 07 mov reg[0ah], 07h ; Port_2_IntCtrl_0 register (PRT2IC0)
41 0717 62 0B 07 mov reg[0bh], 07h ; Port_2_IntCtrl_1 register (PRT2IC1)
42 071A 70 EF M8C_SetBank0
43 071C 62 09 07 mov reg[09h], 07h ; Port_2_IntEn register (PRT2IE)
44 071F 71 10 M8C_SetBank1
45 0721 62 0C 00 mov reg[0ch], 00h ; Port_3_DriveMode_0 register (PRT3DM0)
46 0724 62 0D 03 mov reg[0dh], 03h ; Port_3_DriveMode_1 register (PRT3DM1)
47 0727 70 EF M8C_SetBank0
48 0729 62 0F 03 mov reg[0fh], 03h ; Port_3_DriveMode_2 register (PRT3DM2)
49 072C 62 0E 00 mov reg[0eh], 00h ; Port_3_GlobalSelect register (PRT3GS)
50 072F 71 10 M8C_SetBank1
51 0731 62 0E 00 mov reg[0eh], 00h ; Port_3_IntCtrl_0 register (PRT3IC0)
52 0734 62 0F 00 mov reg[0fh], 00h ; Port_3_IntCtrl_1 register (PRT3IC1)
53 0737 70 EF M8C_SetBank0
54 0739 62 0D 00 mov reg[0dh], 00h ; Port_3_IntEn register (PRT3IE)
55 073C 7F ret
56 073D LoadConfigTBL_hitech_tst_Bank0:
57 ; Global Register values
58 073D 60 0B db 60h, 0bh ; AnalogColumnInputSelect register (AMX_IN)
59 073F 66 00 db 66h, 00h ; AnalogComparatorControl1 register (CMP_CR1)
60 0741 63 15 db 63h, 15h ; AnalogReferenceControl register (ARF_CR)
61 0743 65 00 db 65h, 00h ; AnalogSyncControl register (ASY_CR)
62 0745 E6 02 db e6h, 02h ; DecimatorControl_0 register (DEC_CR0)
63 0747 E7 01 db e7h, 01h ; DecimatorControl_1 register (DEC_CR1)
64 0749 D6 41 db d6h, 41h ; I2CConfig register (I2CCFG)
65 074B B0 00 db b0h, 00h ; Row_0_InputMux register (RDI0RI)
66 074D B1 00 db b1h, 00h ; Row_0_InputSync register (RDI0SYN)
67 074F B2 00 db b2h, 00h ; Row_0_LogicInputAMux register (RDI0IS)
68 0751 B3 C1 db b3h, c1h ; Row_0_LogicSelect_0 register (RDI0LT0)
69 0753 B4 1A db b4h, 1ah ; Row_0_LogicSelect_1 register (RDI0LT1)
70 0755 B5 88 db b5h, 88h ; Row_0_OutputDrive_0 register (RDI0SRO0)
71 0757 B6 CC db b6h, cch ; Row_0_OutputDrive_1 register (RDI0SRO1)
72 0759 69 00 db 69h, 00h ; SARADC_Control_0 register (SARADC_C0)
73 075B 6A 00 db 6ah, 00h ; SARADC_Control_1 register (SARADC_C1)
74 ; Instance name CMPPRG, User Module CMPPRG
75 ; Instance name CMPPRG, Block Name COMP(ACB00)
76 075D 71 1A db 71h, 1ah ;CMPPRG_COMP_CR0(ACB00CR0)
77 075F 72 61 db 72h, 61h ;CMPPRG_COMP_CR1(ACB00CR1)
78 0761 73 40 db 73h, 40h ;CMPPRG_COMP_CR2(ACB00CR2)
79 0763 70 00 db 70h, 00h ;CMPPRG_COMP_CR3(ACB00CR3)
80 ; Instance name DigBuf, User Module DigBuf
81 ; Instance name DigBuf, Block Name DigBuf(DCB02)
82 0765 2B 03 db 2bh, 03h ;DigBuf_CONTROL_REG(DCB02CR0)
83 0767 29 00 db 29h, 00h ;DigBuf_DATA_1_REG(DCB02DR1)
84 0769 2A 00 db 2ah, 00h ;DigBuf_DATA_2_REG(DCB02DR2)
85 ; Instance name EzI2Cs, User Module EzI2Cs
86 ; Instance name PGA, User Module PGA
87 ; Instance name PGA, Block Name GAIN(ACB01)
88 076B 75 1E db 75h, 1eh ;PGA_GAIN_CR0(ACB01CR0)
89 076D 76 21 db 76h, 21h ;PGA_GAIN_CR1(ACB01CR1)
90 076F 77 20 db 77h, 20h ;PGA_GAIN_CR2(ACB01CR2)
91 0771 74 00 db 74h, 00h ;PGA_GAIN_CR3(ACB01CR3)
92 ; Instance name PWM, User Module PWM8
93 ; Instance name PWM, Block Name PWM8(DCB03)
94 0773 2F 00 db 2fh, 00h ;PWM_CONTROL_REG(DCB03CR0)
95 0775 2D FE db 2dh, feh ;PWM_PERIOD_REG(DCB03DR1)
96 0777 2E 14 db 2eh, 14h ;PWM_COMPARE_REG(DCB03DR2)
97 ; Instance name SAR8, User Module SAR8
98 0779 FF db ffh
99 077A LoadConfigTBL_hitech_tst_Bank1:
100 ; Global Register values
101 077A 61 00 db 61h, 00h ; AnalogClockSelect1 register (CLK_CR1)
102 077C 69 00 db 69h, 00h ; AnalogClockSelect2 register (CLK_CR2)
103 077E 60 00 db 60h, 00h ; AnalogColumnClockSelect register (CLK_CR0)
104 0780 62 80 db 62h, 80h ; AnalogIOControl_0 register (ABF_CR0)
105 0782 67 3C db 67h, 3ch ; AnalogLUTControl0 register (ALT_CR0)
106 0784 68 00 db 68h, 00h ; AnalogLUTControl1 register (ALT_CR1)
107 0786 63 00 db 63h, 00h ; AnalogModulatorControl_0 register (AMD_CR0)
108 0788 66 00 db 66h, 00h ; AnalogModulatorControl_1 register (AMD_CR1)
109 078A D1 00 db d1h, 00h ; GlobalDigitalInterconnect_Drive_Even_Input register (GDI_E_IN)
110 078C D3 00 db d3h, 00h ; GlobalDigitalInterconnect_Drive_Even_Output register (GDI_E_OU)
111 078E D0 00 db d0h, 00h ; GlobalDigitalInterconnect_Drive_Odd_Input register (GDI_O_IN)
112 0790 D2 00 db d2h, 00h ; GlobalDigitalInterconnect_Drive_Odd_Output register (GDI_O_OU)
113 0792 E1 4B db e1h, 4bh ; OscillatorControl_1 register (OSC_CR1)
114 0794 E2 00 db e2h, 00h ; OscillatorControl_2 register (OSC_CR2)
115 0796 DF 00 db dfh, 00h ; OscillatorControl_3 register (OSC_CR3)
116 0798 DE 00 db deh, 00h ; OscillatorControl_4 register (OSC_CR4)
117 079A DD 00 db ddh, 00h ; OscillatorGlobalBusEnableControl register (OSC_GO_EN)
118 079C AB 03 db abh, 03h ; SARADC_Control_2 register (SARADC_C2)
119 079E A8 00 db a8h, 00h ; SARADC_TriggerSource register (SARADC_TRS)
120 ; Instance name CMPPRG, User Module CMPPRG
121 ; Instance name CMPPRG, Block Name COMP(ACB00)
122 ; Instance name DigBuf, User Module DigBuf
123 ; Instance name DigBuf, Block Name DigBuf(DCB02)
124 07A0 28 22 db 28h, 22h ;DigBuf_FUNC_REG(DCB02FN)
125 07A2 29 4B db 29h, 4bh ;DigBuf_INPUT_REG(DCB02IN)
126 07A4 2A 6C db 2ah, 6ch ;DigBuf_OUTPUT_REG(DCB02OU)
127 ; Instance name EzI2Cs, User Module EzI2Cs
128 ; Instance name PGA, User Module PGA
129 ; Instance name PGA, Block Name GAIN(ACB01)
130 ; Instance name PWM, User Module PWM8
131 ; Instance name PWM, Block Name PWM8(DCB03)
132 07A6 2C 31 db 2ch, 31h ;PWM_FUNC_REG(DCB03FN)
133 07A8 2D 15 db 2dh, 15h ;PWM_INPUT_REG(DCB03IN)
134 07AA 2E 47 db 2eh, 47h ;PWM_OUTPUT_REG(DCB03OU)
135 ; Instance name SAR8, User Module SAR8
136 07AC FF db ffh
HI-TECH Software Macro Assembler (PSoC MCU) V9.60PL1
Symbol Table Mon Nov 26 12:52:32 2007
LoadConfigTBL_hitech_tst_Bank0 073D LoadConfigTBL_hitech_tst_Bank1 077A MAC_X 00EC
MAC_Y 00ED LoadConfigTBL_hitech_tst_Ordered 06C8 MAC_CL0 00EE
MAC_CL1 00EF FLAG_XIO_MASK 0010
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