📄 psocconfigtbl.lst
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448 0000 VLT_CR_PORLEV: equ 30h ; MASK: Mask for Power on Reset level control
449 0000 VLT_CR_POR_LOW: equ 00h ; Lowest Precision Power-on Reset trip point
450 0000 VLT_CR_POR_MID: equ 10h ; Middle Precision Power-on Reset trip point
451 0000 VLT_CR_POR_HIGH: equ 20h ; Highest Precision Power-on Reset trip point
452 0000 VLT_CR_LVDTBEN: equ 08h ; MASK: Enable the CPU Throttle Back on LVD
453 0000 VLT_CR_VM: equ 07h ; MASK: Mask for Voltage Monitor level setting
454 0000 VLT_CR_3V0_POR: equ 00h ; -- deprecated symbols --
455 0000 VLT_CR_4V5_POR: equ 10h ; deprecated
456 0000 VLT_CR_4V75_POR: equ 20h ; deprecated
457 0000 VLT_CR_DISABLE: equ 30h ; deprecated
458
459 0000 VLT_CMP: equ E4h ; Voltage Monitor Comparators Register (R)
460 0000 VLT_CMP_PUMP: equ 04h ; MASK: Vcc below SMP trip level
461 0000 VLT_CMP_LVD: equ 02h ; MASK: Vcc below LVD trip level
462 0000 VLT_CMP_PPOR: equ 01h ; MASK: Vcc below PPOR trip level
463
464 0000 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (W)
465 0000 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (W)
466 0000 BDG_TR: equ EAh ; Band Gap Trim Register (W)
467 0000 ECO_TR: equ EBh ; External Oscillator Trim Register (W)
468
469 ;;=============================================================================
470 ;; M8C System Macros
471 ;; These macros should be used when their functions are needed.
472 ;;=============================================================================
473
474 ;----------------------------------------------------
475 ; Swapping Register Banks
476 ;----------------------------------------------------
477 macro M8C_SetBank0
478 and F, ~FLAG_XIO_MASK
479 1DCD endm
480
481 macro M8C_SetBank1
482 or F, FLAG_XIO_MASK
483 1DCD endm
484
485 ;----------------------------------------------------
486 ; Global Interrupt Enable/Disable
487 ;----------------------------------------------------
488 macro M8C_EnableGInt
489 or F, FLAG_GLOBAL_IE
490 1DCD endm
491
492 macro M8C_DisableGInt
493 and F, ~FLAG_GLOBAL_IE
494 1DCD endm
495
496 ;----------------------------------------------------
497 ; Enable/Disable Interrupt Mask
498 ;
499 ; Use the following macros to enable/disable
500 ; bits in the Interrupt mask registers,
501 ; INT_MSK0, INT_MSK1 or INT_MSK3.
502 ;
503 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
504 ; M8C_EnableIntMask INT_MSKN, MASK
505 ;
506 ; where INT_MSKN is INT_MSK0, INT_MSK1 or INT_MSK3
507 ; and MASK is the bit set to enable or disable
508 ;----------------------------------------------------
509 ; Disable Interrupt Bit Mask(s)
510 macro M8C_DisableIntMask
511 and reg[@0], ~@1 ; disable specified interrupt enable bit
512 1DCD endm
513
514 ; Enable Interrupt Bit Mask(s)
515 macro M8C_EnableIntMask
516 or reg[@0], @1 ; enable specified interrupt enable bit
517 1DCD endm
518
519 ;----------------------------------------------------
520 ; Clear Posted Interrupt Flag Mask
521 ;
522 ; Use the following macros to clear the
523 ; bits in the Interrupt Clear registers,
524 ; INT_CLR0, INT_CLR1 or INT_CLR3.
525 ; Usage: M8C_ClearIntFlag INT_CLRN, MASK
526 ;
527 ; where INT_MSKN is INT_CLR0, INT_CLR1 or INT_CLR3
528 ; and MASK is the bit set to enable or disable
529 ;----------------------------------------------------
530 macro M8C_ClearIntFlag
531 mov reg[@0], ~@1 ; clear specified interrupt enable bit
532 1DCD endm
533
534 ;----------------------------------------------------
535 ; Power-On Reset & WatchDog Timer Functions
536 ;----------------------------------------------------
537 macro M8C_EnableWatchDog
538 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
539 1DCD endm
540
541 macro M8C_ClearWDT
542 mov reg[RES_WDT], 00h
543 1DCD endm
544
545 macro M8C_ClearWDTAndSleep
546 mov reg[RES_WDT], 38h
547 1DCD endm
548
549 ;----------------------------------------------------
550 ; CPU Stall for Analog PSoC Block Writes
551 ;----------------------------------------------------
552 macro M8C_Stall
553 or reg[ASY_CR], ASY_CR_SYNCEN
554 1DCD endm
555
556 macro M8C_Unstall
557 and reg[ASY_CR], ~ASY_CR_SYNCEN
558 1DCD endm
559
560 ;----------------------------------------------------
561 ; Sleep, CPU Stop & Software Reset
562 ;----------------------------------------------------
563 macro M8C_Sleep
564 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
565 ; The next instruction to be executed depends on the state of the
566 ; various interrupt enable bits. If some interrupts are enabled
567 ; and the global interrupts are disabled, the next instruction will
568 ; be the one that follows the invocation of this macro. If global
569 ; interrupts are also enabled then the next instruction will be
570 ; from the interrupt vector table. If no interrupts are enabled
571 ; then the CPU sleeps forever.
572 1DCD endm
573
574 macro M8C_Stop
575 ; In general, you probably don't want to do this, but here's how:
576 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
577 ; Next instruction to be executed is located in the interrupt
578 ; vector table entry for Power-On Reset.
579 1DCD endm
580
581 macro M8C_Reset
582 ; Restore CPU to the power-on reset state.
583 mov A, 0
584 SSC
585 ; Next non-supervisor instruction will be at interrupt vector 0.
586 1DCD endm
587
588 ;----------------------------------------------------
589 ; ImageCraft Code Compressor Actions
590 ;----------------------------------------------------
591 ; Suspend Code Compressor
592 ; Must not span a RET or RETI instruction
593 ; without resuming code compression
594 macro Suspend_CodeCompressor
595 or F, 0
596 1DCD endm
597
598 ; Resume Code Compression
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