cic512.v

5阶cic滤波器

// 五级CIC抽取12倍实例：
module cic3_decimator(clk, cic_in, cic_out);
parameter	STATE_HOLD = 1'b0, STATE_SAMPLE = 1'b1;
input 		clk;				// 输入时钟	
input [11:0]   cic_in;			// 输入8位数据
output [29:0] cic_out;		// 输出26位数据
reg  state, derived_clk;
reg  [3:0] counter;
wire [29:0] sxtx;		// Sign extended input
reg  [11:0]  x;					// Registered input
reg  [29:0] IntReg0,IntReg1,IntReg2,IntReg3,IntReg4;			// I section 0,1 and 2
reg  [29:0] ComReg11,ComReg12,ComReg13,ComReg21,ComReg22,ComReg23,ComReg31,ComReg32,ComReg33;
reg  [29:0] ComReg41,ComReg42,ComReg43,ComReg51,ComReg52,ComReg53,ComReg;	
// 有限状态机，用于实现下采样
always @(negedge clk) 
begin: FSM_DECIMATOR
	if(counter == 11)
	  begin	
		state <= STATE_SAMPLE;
		derived_clk <= 1;
		counter <= 0;
	  end
	else
	  begin
		state <= STATE_HOLD;
		derived_clk <= 0;
		counter <= counter + 1;
	  end
end
assign sxtx = {{18{x[7]}},x};	// 符号扩展
// 积分器实现模块
always @(posedge clk) 
begin: INTEGRATOR
	x  <= cic_in;				
	IntReg0 <= IntReg0 + sxtx;
	IntReg1 <= IntReg1 + IntReg0;
	IntReg2 <= IntReg2 + IntReg1;
	IntReg3 <= IntReg3 + IntReg2;
	IntReg4 <= IntReg3 + IntReg3;
end
//梳状器实现模块 
always @(posedge clk)
begin:COMB
if(state==STATE_SAMPLE)
begin
    ComReg11 <= IntReg4;
	ComReg12 <= ComReg11;
	ComReg13 <= ComReg12;
	ComReg21 <= ComReg11 - ComReg13;
	ComReg22 <= ComReg21;
	ComReg23 <= ComReg22;
	ComReg31 <= ComReg21 - ComReg23;
	ComReg32 <= ComReg31;
	ComReg33 <= ComReg32;
	ComReg41  <= ComReg31 - ComReg33;
	ComReg42 <= ComReg41;
	ComReg43 <= ComReg42;
	ComReg41 <= ComReg41 - ComReg43;
	ComReg52 <= ComReg51;
	ComReg53 <= ComReg52;
	ComReg    <= ComReg51 - ComReg53;
end
end
assign cic_out = ComReg;		//输出
endmodule