automake.log

lattice xp2 系列开发板带源码

Signal rstn_c is selected as Global Set/Reset.
Starting Placer Phase 0.
.......
Finished Placer Phase 0.  REAL time: 12 secs 

Starting Placer Phase 1.
Placer score = 205170.
........................
Placer score = 70452.
Finished Placer Phase 1.  REAL time: 17 secs 

Starting Placer Phase 2.
.
Placer score =  57923
Finished Placer Phase 2.  REAL time: 17 secs 


------------------ Clock Report ------------------

Global Clock Resources:
  CLK_PIN    : 0 out of 8 (0%)
  General PIO: 1 out of 364 (0%)
  PLL        : 0 out of 4 (0%)
  DCS        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "clk_c" from PIO "52", driver "clk", clk load = 31

  PRIMARY  : 1 out of 8 (12%)
     DCS   : 0 out of 2 (0%)
  SECONDARY: 0 out of 4 (0%)

Edge Clocks:
  No edge clock selected

--------------- End of Clock Report ---------------


I/O Usage Summary:
   59 out of 364 (16%) PIO sites used.
   59 out of 146 (40%) bonded PIO sites used.
   Number of PIO comps: 59; differential: 0
   Number of Vref pins used: 0


DSP Utilization Summary:
-------------------------------------
DSP Block #:              1 2 3 4 5
# of MULT36X36B                    
# of MULT18X18B                    
# of MULT18X18MACB                 
# of MULT18X18ADDSUBB              
# of MULT18X18ADDSUBSUMB           
# of MULT9X9B                      
# of MULT9X9ADDSUBB                
# of MULT9X9ADDSUBSUMB             

Total placer CPU time: 15 secs 

Dumping design to file xp2_demo.dir/5_1.ncd.

0 connections routed; 297 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net clk_c is not placed on one
          of the PIO sites which are dedicated for primary clocks.  This
          primary clock will be routed to a H-spine through general routing
          resource or be routed as secondary clock and may suffer from
          excessive delay or skew.
Completed router resource preassignment. Real time: 24 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
297 successful; 0 unrouted; (32745) real time: 24 secs 
Dumping design to file xp2_demo.dir/5_1.ncd.
End of iteration 2
297 successful; 0 unrouted; (32492) real time: 26 secs 
Dumping design to file xp2_demo.dir/5_1.ncd.
End of iteration 3
297 successful; 0 unrouted; (32492) real time: 28 secs 
End of iteration 4
297 successful; 0 unrouted; (32492) real time: 33 secs 
End of iteration 5
297 successful; 0 unrouted; (32492) real time: 39 secs 
End of iteration 6
297 successful; 0 unrouted; (32492) real time: 45 secs 
Total CPU time 43 secs 
Total REAL time: 45 secs 
Completely routed.
End of route.  297 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights reserved.
Exiting par with exit code 0
Exiting multipar with exit code 0
Done: completed successfully.

Starting: 'E:\ispTOOLS7_0\ispcpld\bin\checkpoint.exe -p -f "xp2_demo.cmp" -f "xp2_demo.cm2" -arch LatticeXP2 "xp2_demo.ncd" -l 60'


---- Checkpoint Tool Log File ----

==== Trace Standard Out ====
trce:  version ispLever_v70_Prod_Build (55)
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
     Copyright (c) 1995 AT&T Corp.   All rights reserved.
     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
     Copyright (c) 2001 Agere Systems   All rights reserved.
     Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights
     reserved.

Loading design for application trce from file xp2_demo.ncd.
Design name: Multi_top
NCD version: 3.2
Vendor:      LATTICE
Device:      LFXP2-17E
Package:     PQFP208
Speed:       5
Loading device for application trce from file 'mg5a50x47.nph' in
environment: E:/ispTOOLS7_0/ispfpga.
Package: Version 1.60, Status: FINAL
Speed Hardware Data: version 1.67.1.5
--------------------------------------------------------------------------------
Lattice TRACE Report, Version ispLever_v70_SP2_Build (24)
Tue Jan 15 11:52:29 2008

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -o checkpnt.twr xp2_demo.ncd xp2_demo.prf 
Design file:     xp2_demo.ncd
Preference file: xp2_demo.prf
Device,speed:    LFXP2-17E,5
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------



Timing summary:
---------------

Timing errors: 62  Score: 32492
Cumulative negative slack: 32492

Constraints cover 649 paths, 1 nets, and 181 connections (60.9% coverage)

--------------------------------------------------------------------------------

Total time: 10 secs 
==== End of Trace Standard Out ====

*********************************
Par checkpoint failed.
Design does not meet timing.
*********************************
 Process Continuing ...

Done: completed successfully.

Starting: 'E:\ispTOOLS7_0\ispfpga\bin\nt\bitgen.exe  -f "xp2_demo.t2b" -w "xp2_demo.ncd" -jedec -e -s "xp2_demo.sec" -k "xp2_demo.bek" "xp2_demo.prf"'



BITGEN: Bitstream Generator ispLever_v70_SP2_Build (24)
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights reserved.


Loading design for application Bitgen from file xp2_demo.ncd.
Design name: Multi_top
NCD version: 3.2
Vendor:      LATTICE
Device:      LFXP2-17E
Package:     PQFP208
Speed:       5
Loading device for application Bitgen from file 'mg5a50x47.nph' in
environment: E:/ispTOOLS7_0/ispfpga.
Package: Version 1.60, Status: FINAL
Speed Hardware Data: version 1.67.1.5

Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from xp2_demo.prf...

Preference Summary:
+---------------------------------+---------------------------------+
|  Preference                     |  Current Setting                |
+---------------------------------+---------------------------------+
|                         RamCfg  |                        Reset**  |
+---------------------------------+---------------------------------+
|                        DONE_EX  |                          OFF**  |
+---------------------------------+---------------------------------+
|                        DONE_OD  |                           ON**  |
+---------------------------------+---------------------------------+
|                     MCCLK_FREQ  |                          3.1**  |
+---------------------------------+---------------------------------+
|                  CONFIG_SECURE  |                          OFF**  |
+---------------------------------+---------------------------------+
|                        WAKE_UP  |                           21**  |
+---------------------------------+---------------------------------+
|                   WAKE_ON_LOCK  |                          OFF**  |
+---------------------------------+---------------------------------+
|                          INBUF  |                           ON**  |
+---------------------------------+---------------------------------+
|                     ENABLE_NDR  |                          OFF**  |
+---------------------------------+---------------------------------+
|                        MY_ASSP  |                          OFF**  |
+---------------------------------+---------------------------------+
|               ONE_TIME_PROGRAM  |                          OFF**  |
+---------------------------------+---------------------------------+
|                 SLAVE_SPI_PORT  |                      DISABLE**  |
+---------------------------------+---------------------------------+
|                MASTER_SPI_PORT  |                      DISABLE**  |
+---------------------------------+---------------------------------+
|                     DisableUES  |                        FALSE**  |
+---------------------------------+---------------------------------+
 *  Default setting.
 ** The specified setting matches the default setting.


Creating bit map...
Saving bit stream in "xp2_demo.jed".
Done: completed successfully.