automake.log

lattice xp2 系列开发板带源码

ispLEVER Auto-Make Log File
---------------------------

Updating: Generate Data File (JEDEC)
Start to record tcl script...
Finished recording TCL script.

Starting: 'E:\ispTOOLS7_0\ispfpga\bin\nt\map.exe  -a LatticeXP2 -p LFXP2-17E -t PQFP208 -s 5 "xp2_demo.ngd" -o "xp2_demo_map.ncd" -mp "xp2_demo.mrp" "xp2_demo.lpf"'

map:  version ispLever_v70_Prod_Build (55)
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
     Copyright (c) 1995 AT&T Corp.   All rights reserved.
     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
     Copyright (c) 2001 Agere Systems   All rights reserved.
     Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights
     reserved.
   Process the file: xp2_demo.ngd
   Picdevice="LFXP2-17E"
   Pictype="PQFP208"
   Picspeed=5
   Remove unused logic
   Do not produce over sized NCDs.
Part used: LFXP2-17EPQFP208, Speed used: 5.
WARNING - map: Semantic Error: cnt_20 matches no nets in the design. 
     Occurred in "USE PRIMARY NET "cnt_20" ;
     ".  Disabled this preference.
WARNING - map: Preference parsing results:  1 semantic error detected
WARNING - map: There are errors in the preference file, "xp2_demo.lpf".
Loading device for application map from file 'mg5a50x47.nph' in
     environment: E:/ispTOOLS7_0/ispfpga.
Package: Version 1.60, Status: FINAL

Running general design DRC...
Removing unused logic...
Optimizing...
Absorbing 44 CCU2 constant inputs...



Design Summary:
   Number of registers:    44
      PFU registers:    28
      PIO registers:    16
   Number of SLICEs:            39 out of  8280 (0%)
      SLICEs(logic/ROM):        39 out of  6795 (1%)
      SLICEs(logic/ROM/RAM):     0 out of  1485 (0%)
          As RAM:            0 out of  1485 (0%)
          As Logic/ROM:      0 out of  1485 (0%)
   Number of logic LUT4s:      33
   Number of distributed RAM:   0 (0 LUT4s)
   Number of ripple logic:     15 (30 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:      63
   Number of external PIOs: 59 out of 146 (40%)
   Number of PIO IDDR/ODDR:     0
   Number of PIO FIXEDDELAY:    0
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of 3-state buffers:   0
   Number of PLLs:  0 out of 4 (0%)
   Number of block RAMs:  0 out of 15 (0%)
   Number of CLKDIVs:  0 out of 2 (0%)
   Number of GSRs:  1 out of 1 (100%)
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.

DSP Component Details --
------------------------

   Number Of Mapped DSP Components:
   --------------------------------
   MULT36X36B          0
   MULT18X18B          0
   MULT18X18MACB       0
   MULT18X18ADDSUBB    0
   MULT18X18ADDSUBSUMB 0
   MULT9X9B            0
   MULT9X9ADDSUBB      0
   MULT9X9ADDSUBSUMB   0
   --------------------------------
   Number of clocks:  1
     Net clk_c: 31 loads, 31 rising, 0 falling (Driver: PIO clk )
   Number of Clock Enables:  1
     Net rstn_c: 8 loads, 0 LSLICEs
   Number of LSRs:  0
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net ld_c: 39 loads
     Net GND: 25 loads
     Net q_tmp_25: 14 loads
     Net q_tmp_27: 12 loads
     Net q_tmp_26: 11 loads
     Net VCC: 10 loads
     Net rstn_c: 9 loads
     Net q_tmp_24: 5 loads
     Net seg_data_19_0_s_0: 4 loads
     Net seg_data_18_7_0__N_2: 3 loads
   Number of warnings:  0
   Number of errors:    0

Total CPU Time: 1 secs  
Total REAL Time: 3 secs  
Peak Memory Usage: 69 MB

WARNING - map: There are semantic errors in the preference file,
     "xp2_demo.prf".
Dumping design to file xp2_demo_map.ncd.
Done: completed successfully.

Starting: 'E:\ispTOOLS7_0\ispcpld\bin\checkpoint.exe -m -f "xp2_demo.cmm" -f "xp2_demo.cm2" -arch LatticeXP2 "xp2_demo_map.ncd"'


---- Checkpoint Tool Log File ----
Logic percent not specified. Using 50 logic percent for architecture LatticeXP2.

==== Trace Standard Out ====
trce:  version ispLever_v70_Prod_Build (55)
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
     Copyright (c) 1995 AT&T Corp.   All rights reserved.
     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
     Copyright (c) 2001 Agere Systems   All rights reserved.
     Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights
     reserved.

Loading design for application trce from file xp2_demo_map.ncd.
Design name: Multi_top
NCD version: 3.2
Vendor:      LATTICE
Device:      LFXP2-17E
Package:     PQFP208
Speed:       5
Loading device for application trce from file 'mg5a50x47.nph' in
environment: E:/ispTOOLS7_0/ispfpga.
Package: Version 1.60, Status: FINAL
Speed Hardware Data: version 1.67.1.5
--------------------------------------------------------------------------------
Lattice TRACE Report, Version ispLever_v70_SP2_Build (24)
Tue Jan 15 11:51:31 2008

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -gt -o checkpnt.twr xp2_demo_map.ncd xp2_demo.prf 
Design file:     xp2_demo_map.ncd
Preference file: xp2_demo.prf
Device,speed:    LFXP2-17E,5
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------



Timing summary:
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 649 paths, 1 nets, and 165 connections (55.6% coverage)

--------------------------------------------------------------------------------

Total time: 10 secs 
==== End of Trace Standard Out ====

*********************************
Map checkpoint failed.
Design's logic delay (58 percent of total delay) 
exceeds the 50 percent limit set in the map checkpoint options
*********************************
 Process Continuing ...

Done: completed successfully.

Starting: 'E:\ispTOOLS7_0\ispcpld\bin\multipar.exe -p xp2_demo.p2t -f "xp2_demo.p3t" "xp2_demo_map.ncd" "xp2_demo.ncd"'

---- Multipar Tool ----

Removing old design directory at request of -rem command line option to
this program.
Running par. Please wait . . .

Lattice Place and Route Report for Design "xp2_demo_map.ncd"
Tue Jan 15 11:51:33 2008

PAR: Place And Route ispLever_v70_Prod_Build (55).
Command line: E:/ispTOOLS7_0/ispfpga\bin\nt\par -f xp2_demo.p2t xp2_demo_map.ncd xp2_demo.dir
xp2_demo.prf
Preference file: xp2_demo.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file xp2_demo_map.ncd.
Design name: Multi_top
NCD version: 3.2
Vendor:      LATTICE
Device:      LFXP2-17E
Package:     PQFP208
Speed:       5
Loading device for application par from file 'mg5a50x47.nph' in
environment: E:/ispTOOLS7_0/ispfpga.
Package: Version 1.60, Status: FINAL
Speed Hardware Data: version 1.67.1.5


Ignore Preference Error(s):  True
Dumping design to file C:/DOCUME~1/DINOSU~1/LOCALS~1/Temp/neo_2.
Device utilization summary:


   PIO               59/364          16% used
                     59/146          40% bonded

   IOLOGIC           16/364           4% used
   SLICE             39/8280         <1% used

   GSR                1/1           100% used


Number of Signals: 126
Number of Connections: 297

Pin Constraint Summary:
   38 out of 59 pins locked (64% locked).

The following 1 signal is selected to use the primary clock routing resource:
    clk_c (driver: clk, clk load #: 31)

WARNING - par: Signal "clk_c" is selected to use Primary clock resources;
          however its driver comp "clk" is located at "52", which is not a
          dedicated pin for connecting to Primary clock resources.  General
          routing has to be used to route this signal, and it may suffer
          from excessive delay or skew.
No signal is selected as DCS clock.

No signal is selected as secondary clock.