multi_top_la0_inst.v

来自「lattice xp2 系列开发板带源码」· Verilog 代码 · 共 27 行

//=============================================================================
// Verilog module generated by IPExpress    11/13/2007    09:49:52         
// Filename: Multi_top_LA0_inst.v                                          
// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved.   
//=============================================================================

/* WARNING - Changes to this file should be performed by re-running IPexpress
or modifying the .LPC file and regenerating the core.  Other changes may lead
to inconsistent simulation and/or implemenation results */

Multi_top_LA0 (
    .clk		(clk),
    .reset_n		(reset_n),
    .jtck		(jtck),
    .jrstn		(jrstn),
    .jce2		(jce2),
    .jtdi		(jtdi),
    .er2_tdo		(er2_tdo),
    .jshift		(jshift),
    .jupdate		(jupdate),
    .trigger_din_0	(trigger_din_0),
    .trigger_din_1	(trigger_din_1),
    .trace_din		(trace_din),
    .ip_enable    	(ip_enable)
);