data_multi_tmpl.vhd

来自「lattice xp2 系列开发板带源码」· VHDL 代码 · 共 17 行

-- VHDL module instantiation generated by SCUBA ispLever_v70_SP1_Build (25)
-- Module  Version: 2.3
-- Mon Nov 12 11:34:01 2007

-- parameterized module component declaration
component Data_multi
    port (CLK0: in  std_logic; RST0: in  std_logic; 
        A: in  std_logic_vector(15 downto 0); 
        B: in  std_logic_vector(3 downto 0); 
        P: out  std_logic_vector(19 downto 0));
end component;

-- parameterized module component instance
__ : Data_multi
    port map (CLK0=>__, RST0=>__, A(15 downto 0)=>__, B(3 downto 0)=>__, 
        P(19 downto 0)=>__);