📄 multi_top.log
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#Build: Synplify for Lattice 9.0L1, Build 024R, Nov 13 2007
#install: E:\ISPTOOLS7_0\SYNPBASE
#OS: Windows XP 5.1
#Hostname: DINO
#Implementation: xp2_demo
#Tue Jan 15 11:47:27 2008
$ Start of Compile
#Tue Jan 15 11:47:27 2008
Synplicity VHDL Compiler, version 1.0, Build 157R, built Nov 13 2007
Copyright (C) 1994-2007, Synplicity Inc. All Rights Reserved
@N: CD720 :"E:\ISPTOOLS7_0\SYNPBASE\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\temp\xp2_demo\multi_top.vhd":6:7:6:15|Top entity is set to Multi_top.
VHDL syntax check successful!
@N: CD630 :"C:\temp\xp2_demo\multi_top.vhd":6:7:6:15|Synthesizing work.multi_top.multi_top_arch
@W: CD638 :"C:\temp\xp2_demo\multi_top.vhd":45:7:45:10|Signal qout is undriven
Post processing for work.multi_top.multi_top_arch
@W: CL240 :"C:\temp\xp2_demo\multi_top.vhd":11:3:11:11|Multi_out is not assigned a value (floating) - a simulation mismatch is possible
@W: CL169 :"C:\temp\xp2_demo\multi_top.vhd":61:1:61:2|Pruning Register cnt_d0(3 downto 0)
@W: CL169 :"C:\temp\xp2_demo\multi_top.vhd":61:1:61:2|Pruning Register cnt(3 downto 0)
@W: CL112 :"C:\temp\xp2_demo\multi_top.vhd":89:1:89:2|Feedback mux created for signal seg_data[7:0]. Did you forget the set/reset assignment for this signal?
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 15 11:47:28 2008
###########################################################]
Total runtime: 00h:00m:01s realtime
Synplicity Generic Technology Mapper, Version 9.0.0, Build 139R, Built Nov 13 2007 20:48:37
Copyright (C) 1994-2007, Synplicity Inc. All Rights Reserved
Product Version Version 9.0L1
@N: MF249 |Running in 32-bit mode.
@N: FA239 :"c:\temp\xp2_demo\multi_top.vhd":98:3:98:6|Rom seg_data_18[7:0] mapped in logic.
@N: MO106 :"c:\temp\xp2_demo\multi_top.vhd":98:3:98:6|Found ROM, 'seg_data_18[7:0]', 16 words by 8 bits
RTL optimization done.
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 52MB)
@N:"c:\temp\xp2_demo\multi_top.vhd":89:1:89:2|Found counter in view:work.Multi_top(multi_top_arch) inst q_tmp[27:0]
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)
Clock Buffers:
Inserting Clock buffer for port clk, TNM=clk
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 52MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)
Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)
Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -1.36ns 32 / 44
2 0h:00m:00s -1.36ns 32 / 44
3 0h:00m:00s -1.36ns 32 / 44
------------------------------------------------------------
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -1.36ns 32 / 44
Timing driven replication report
No replication required.
2 0h:00m:00s -1.36ns 32 / 44
3 0h:00m:00s -1.36ns 32 / 44
4 0h:00m:00s -1.36ns 32 / 44
------------------------------------------------------------
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -1.36ns 32 / 44
Timing driven replication report
No replication required.
2 0h:00m:00s -1.36ns 32 / 44
3 0h:00m:00s -1.36ns 32 / 44
4 0h:00m:00s -1.36ns 32 / 44
------------------------------------------------------------
Net buffering Report for view:work.Multi_top(multi_top_arch):
No nets needed buffering.
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)
Warning: Forcing use of GSR for flip-flops and
latches that do not specify sets or resets
work.Multi_top(multi_top_arch)-seg_data[7]
work.Multi_top(multi_top_arch)-seg_data[6]
work.Multi_top(multi_top_arch)-seg_data[5]
work.Multi_top(multi_top_arch)-seg_data[4]
work.Multi_top(multi_top_arch)-seg_data[3]
work.Multi_top(multi_top_arch)-seg_data[2]
work.Multi_top(multi_top_arch)-seg_data[1]
work.Multi_top(multi_top_arch)-seg_data[0]
Found clock Multi_top|clk with period 5.00ns
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jan 15 11:47:31 2008
#
Top view: Multi_top
Requested Frequency: 200.0 MHz
Wire load mode: top
Paths requested: 3
Constraint File(s):
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
Performance Summary
*******************
Worst slack in design: -1.186
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------
Multi_top|clk 200.0 MHz 161.7 MHz 5.000 6.186 -1.186 inferred Inferred_clkgroup_0
System 200.0 MHz 210.2 MHz 5.000 4.757 0.243 system default_clkgroup
======================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
---------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
---------------------------------------------------------------------------------------------------------------------
Multi_top|clk Multi_top|clk | 5.000 -1.186 | No paths - | No paths - | No paths -
=====================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
-------------------------------------------------------------------------------
clk NA NA NA NA NA
d[0] System (rising) NA 0.000 0.038
d[1] System (rising) NA 0.000 0.126
d[2] System (rising) NA 0.000 0.126
d[3] System (rising) NA 0.000 0.214
d[4] System (rising) NA 0.000 0.214
d[5] System (rising) NA 0.000 0.302
d[6] System (rising) NA 0.000 0.302
d[7] System (rising) NA 0.000 1.307
ld System (rising) NA 0.000 -1.186
mii_rx_er System (rising) NA 0.000 0.243
rstn System (rising) NA 0.000 2.465
===============================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
--------------------------------------------------------------------------------------------
Multi_out[0] NA NA NA NA NA
Multi_out[1] NA NA NA NA NA
Multi_out[2] NA NA NA NA NA
Multi_out[3] NA NA NA NA NA
Multi_out[4] NA NA NA NA NA
Multi_out[5] NA NA NA NA NA
Multi_out[6] NA NA NA NA NA
Multi_out[7] NA NA NA NA NA
Multi_out[8] NA NA NA NA NA
Multi_out[9] NA NA NA NA NA
Multi_out[10] NA NA NA NA NA
Multi_out[11] NA NA NA NA NA
Multi_out[12] NA NA NA NA NA
Multi_out[13] NA NA NA NA NA
Multi_out[14] NA NA NA NA NA
Multi_out[15] NA NA NA NA NA
Multi_out[16] NA NA NA NA NA
Multi_out[17] NA NA NA NA NA
Multi_out[18] NA NA NA NA NA
Multi_out[19] NA NA NA NA NA
mii_tx_er System (rising) NA 4.757 5.000
mii_txen NA NA NA NA NA
phya[0] NA NA NA NA NA
phya[1] NA NA NA NA NA
phya[2] NA NA NA NA NA
phya[3] NA NA NA NA NA
phya[4] NA NA NA NA NA
q[0] Multi_top|clk (rising) NA 4.187 5.000
q[1] Multi_top|clk (rising) NA 4.187 5.000
q[2] Multi_top|clk (rising) NA 4.187 5.000
q[3] Multi_top|clk (rising) NA 4.187 5.000
q[4] Multi_top|clk (rising) NA 4.187 5.000
q[5] Multi_top|clk (rising) NA 4.187 5.000
q[6] Multi_top|clk (rising) NA 4.187 5.000
q[7] Multi_top|clk (rising) NA 4.187 5.000
seg_data_out[0] Multi_top|clk (rising) NA 4.187 5.000
seg_data_out[1] Multi_top|clk (rising) NA 4.187 5.000
seg_data_out[2] Multi_top|clk (rising) NA 4.187 5.000
seg_data_out[3] Multi_top|clk (rising) NA 4.187 5.000
seg_data_out[4] Multi_top|clk (rising) NA 4.187 5.000
seg_data_out[5] Multi_top|clk (rising) NA 4.187 5.000
seg_data_out[6] Multi_top|clk (rising) NA 4.187 5.000
seg_data_out[7] Multi_top|clk (rising) NA 4.187 5.000
sel_out[0] NA NA NA NA NA
sel_out[1] NA NA NA NA NA
sel_out[2] NA NA NA NA NA
sel_out[3] NA NA NA NA NA
============================================================================================
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report
Part: lfxp2_17e-5
Register bits: 44 of 16560 (0%)
I/O cells: 59
Details:
CCU2B: 15
FD1S3AX: 28
GSR: 1
IB: 12
INV: 8
OB: 47
OFS1P3BX: 8
OFS1P3DX: 8
ORCALUT4: 23
PFUMX: 5
VHI: 1
VLO: 1
Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 51MB peak: 52MB)
Writing Analyst data base C:\temp\xp2_demo\Multi_top.srm
@N: MF203 |Set autoconstraint_io
Writing EDIF Netlist and constraint files
@N: MF203 |Set autoconstraint_io
Version 9.0L1
Writing Verilog Simulation files
@N: MF203 |Set autoconstraint_io
Writing VHDL Simulation files
@N: MF203 |Set autoconstraint_io
@N: MF203 |Set autoconstraint_io
Mapper successful!
Process took 0h:00m:03s realtime, 0h:00m:02s cputime
# Tue Jan 15 11:47:33 2008
###########################################################]
Total runtime: 00h:00m:07s realtime
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