📄 multi_top.vhm
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LD_PAD: IB port map (
I => ld,
O => LD_C);
\MULTI_OUT_PAD[19]\: OB port map (
I => GND,
O => Multi_out(19));
\MULTI_OUT_PAD[18]\: OB port map (
I => GND,
O => Multi_out(18));
\MULTI_OUT_PAD[17]\: OB port map (
I => GND,
O => Multi_out(17));
\MULTI_OUT_PAD[16]\: OB port map (
I => GND,
O => Multi_out(16));
\MULTI_OUT_PAD[15]\: OB port map (
I => GND,
O => Multi_out(15));
\MULTI_OUT_PAD[14]\: OB port map (
I => GND,
O => Multi_out(14));
\MULTI_OUT_PAD[13]\: OB port map (
I => GND,
O => Multi_out(13));
\MULTI_OUT_PAD[12]\: OB port map (
I => GND,
O => Multi_out(12));
\MULTI_OUT_PAD[11]\: OB port map (
I => GND,
O => Multi_out(11));
\MULTI_OUT_PAD[10]\: OB port map (
I => GND,
O => Multi_out(10));
\MULTI_OUT_PAD[9]\: OB port map (
I => GND,
O => Multi_out(9));
\MULTI_OUT_PAD[8]\: OB port map (
I => GND,
O => Multi_out(8));
\MULTI_OUT_PAD[7]\: OB port map (
I => GND,
O => Multi_out(7));
\MULTI_OUT_PAD[6]\: OB port map (
I => GND,
O => Multi_out(6));
\MULTI_OUT_PAD[5]\: OB port map (
I => GND,
O => Multi_out(5));
\MULTI_OUT_PAD[4]\: OB port map (
I => GND,
O => Multi_out(4));
\MULTI_OUT_PAD[3]\: OB port map (
I => GND,
O => Multi_out(3));
\MULTI_OUT_PAD[2]\: OB port map (
I => GND,
O => Multi_out(2));
\MULTI_OUT_PAD[1]\: OB port map (
I => GND,
O => Multi_out(1));
\MULTI_OUT_PAD[0]\: OB port map (
I => GND,
O => Multi_out(0));
RSTN_PAD: IB port map (
I => rstn,
O => RSTN_C);
CLK_PAD: IB port map (
I => clk,
O => CLK_C);
\SEG_DATA_18_7_0_.N_2\ <= Q_TMP(26) and not Q_TMP(27);
\SEG_DATA_18_7_0_.N_17\ <= not Q_TMP(26) and not Q_TMP(27);
\SEG_DATA_18_7_0_.N_4\ <= (not Q_TMP(26) and not Q_TMP(27)) or
(Q_TMP(26) and Q_TMP(27));
SEG_DATA_19_0_S(0) <= LD_C and Q_TMP(24);
SEG_DATA_19_0_S(3) <= LD_C and not Q_TMP(24);
SEG_DATA_19(7) <= (LD_C and not Q_TMP(24)) or
(D_C(7) and not LD_C);
\SEG_DATA_18_7_0_.N_20\ <= (not Q_TMP(27)) or
(not Q_TMP(25) and not Q_TMP(26));
\SEG_DATA_18_7_0_.N_18\ <= (Q_TMP(25) and not Q_TMP(26)) or
(not Q_TMP(25) and Q_TMP(26)) or
(not Q_TMP(26) and Q_TMP(27));
\SEG_DATA_18_7_0_.N_16\ <= (not Q_TMP(25) and Q_TMP(26) and not Q_TMP(27)) or
(Q_TMP(25) and not Q_TMP(26) and Q_TMP(27));
\SEG_DATA_18_7_0_.N_11\ <= (not Q_TMP(25) and Q_TMP(26) and not Q_TMP(27)) or
(Q_TMP(25) and Q_TMP(27));
\SEG_DATA_18_7_0_.N_9\ <= (not Q_TMP(26)) or
(not Q_TMP(25) and not Q_TMP(27));
\SEG_DATA_18_7_0_.N_15\ <= (not Q_TMP(25) and not Q_TMP(27)) or
(Q_TMP(24) and not Q_TMP(27)) or
(Q_TMP(26) and not Q_TMP(27)) or
(not Q_TMP(26) and Q_TMP(27)) or
(Q_TMP(24) and not Q_TMP(25));
SEG_DATA_19_0_D(1) <= (LD_C and not \SEG_DATA_18_7_0_.N_9\) or
(D_C(1) and not LD_C);
SEG_DATA_19_0_D(3) <= (LD_C and not \SEG_DATA_18_7_0_.N_18\) or
(D_C(3) and not LD_C);
SEG_DATA_19_0_D(4) <= (D_C(4) and not LD_C) or
(D_C(4) and \SEG_DATA_18_7_0_.N_20\) or
(LD_C and \SEG_DATA_18_7_0_.N_20\);
SEG_DATA_19(2) <= (LD_C and not \SEG_DATA_18_7_0_.N_15\) or
(D_C(2) and not LD_C);
SEG_DATA_19_0_AM(0) <= (D_C(0) and not LD_C) or
(D_C(0) and not Q_TMP(25) and \SEG_DATA_18_7_0_.N_2\) or
(LD_C and not Q_TMP(25) and \SEG_DATA_18_7_0_.N_2\);
SEG_DATA_19_0_BM(0) <= (not Q_TMP(25) and not Q_TMP(26) and not Q_TMP(27)) or
(Q_TMP(25) and not Q_TMP(26) and Q_TMP(27)) or
(not Q_TMP(25) and Q_TMP(26) and Q_TMP(27));
\SEG_DATA_19_0[0]\: PFUMX port map (
ALUT => SEG_DATA_19_0_BM(0),
BLUT => SEG_DATA_19_0_AM(0),
C0 => SEG_DATA_19_0_S(0),
Z => SEG_DATA_19(0));
SEG_DATA_19_0_AM(5) <= (D_C(5) and not LD_C) or
(D_C(5) and Q_TMP(25) and \SEG_DATA_18_7_0_.N_17\) or
(LD_C and Q_TMP(25) and \SEG_DATA_18_7_0_.N_17\);
SEG_DATA_19_0_BM(5) <= (Q_TMP(25) and not Q_TMP(27)) or
(not Q_TMP(27) and \SEG_DATA_18_7_0_.N_4\) or
(not Q_TMP(25) and \SEG_DATA_18_7_0_.N_4\);
\SEG_DATA_19_0[5]\: PFUMX port map (
ALUT => SEG_DATA_19_0_BM(5),
BLUT => SEG_DATA_19_0_AM(5),
C0 => SEG_DATA_19_0_S(0),
Z => SEG_DATA_19(5));
SEG_DATA_19_0_AM(6) <= (D_C(6) and not LD_C) or
(D_C(6) and not Q_TMP(25) and \SEG_DATA_18_7_0_.N_4\) or
(LD_C and not Q_TMP(25) and \SEG_DATA_18_7_0_.N_4\);
SEG_DATA_19_0_BM(6) <= (Q_TMP(25) and \SEG_DATA_18_7_0_.N_2\) or
(not Q_TMP(25) and \SEG_DATA_18_7_0_.N_17\);
\SEG_DATA_19_0[6]\: PFUMX port map (
ALUT => SEG_DATA_19_0_BM(6),
BLUT => SEG_DATA_19_0_AM(6),
C0 => SEG_DATA_19_0_S(0),
Z => SEG_DATA_19(6));
SEG_DATA_19(4) <= (not SEG_DATA_19_0_S(3) and SEG_DATA_19_0_D(4)) or
(SEG_DATA_19_0_S(3) and not Q_TMP(25) and \SEG_DATA_18_7_0_.N_2\);
\SEG_DATA_19_0[1]\: PFUMX port map (
ALUT => \SEG_DATA_18_7_0_.N_11\,
BLUT => SEG_DATA_19_0_D(1),
C0 => SEG_DATA_19_0_S(0),
Z => SEG_DATA_19(1));
\SEG_DATA_19_0[3]\: PFUMX port map (
ALUT => \SEG_DATA_18_7_0_.N_16\,
BLUT => SEG_DATA_19_0_D(3),
C0 => SEG_DATA_19_0_S(3),
Z => SEG_DATA_19(3));
\Q_TMP_S_0[27]\: CCU2B
generic map(
INIT0 => "0xe40a",
INIT1 => "0x0a0c",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => D_C(7),
C0 => Q_TMP(27),
D0 => VCC,
A1 => GND,
B1 => GND,
C1 => GND,
D1 => VCC,
CIN => Q_TMP_CRY(26),
COUT => Q_TMP_S_0_COUT(27),
S0 => Q_TMP_S(27),
S1 => Q_TMP_S_0_S1(27));
\Q_TMP_CRY_0[25]\: CCU2B
generic map(
INIT0 => "0xe400",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => D_C(5),
C0 => Q_TMP(25),
D0 => VCC,
A1 => LD_C,
B1 => D_C(6),
C1 => Q_TMP(26),
D1 => VCC,
CIN => Q_TMP_CRY(24),
COUT => Q_TMP_CRY(26),
S0 => Q_TMP_S(25),
S1 => Q_TMP_S(26));
\Q_TMP_CRY_0[23]\: CCU2B
generic map(
INIT0 => "0xe400",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => D_C(3),
C0 => Q_TMP(23),
D0 => VCC,
A1 => LD_C,
B1 => D_C(4),
C1 => Q_TMP(24),
D1 => VCC,
CIN => Q_TMP_CRY(22),
COUT => Q_TMP_CRY(24),
S0 => Q_TMP_S(23),
S1 => Q_TMP_S(24));
\Q_TMP_CRY_0[21]\: CCU2B
generic map(
INIT0 => "0xe400",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => D_C(1),
C0 => Q_TMP(21),
D0 => VCC,
A1 => LD_C,
B1 => D_C(2),
C1 => Q_TMP(22),
D1 => VCC,
CIN => Q_TMP_CRY(20),
COUT => Q_TMP_CRY(22),
S0 => Q_TMP_S(21),
S1 => Q_TMP_S(22));
\Q_TMP_CRY_0[19]\: CCU2B
generic map(
INIT0 => "0xe400",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => GND,
C0 => Q_TMP(19),
D0 => VCC,
A1 => LD_C,
B1 => D_C(0),
C1 => Q_TMP(20),
D1 => VCC,
CIN => Q_TMP_CRY(18),
COUT => Q_TMP_CRY(20),
S0 => Q_TMP_S(19),
S1 => Q_TMP_S(20));
\Q_TMP_CRY_0[17]\: CCU2B
generic map(
INIT0 => "0xe400",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => GND,
C0 => Q_TMP(17),
D0 => VCC,
A1 => LD_C,
B1 => GND,
C1 => Q_TMP(18),
D1 => VCC,
CIN => Q_TMP_CRY(16),
COUT => Q_TMP_CRY(18),
S0 => Q_TMP_S(17),
S1 => Q_TMP_S(18));
\Q_TMP_CRY_0[15]\: CCU2B
generic map(
INIT0 => "0xe400",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => GND,
C0 => Q_TMP(15),
D0 => VCC,
A1 => LD_C,
B1 => GND,
C1 => Q_TMP(16),
D1 => VCC,
CIN => Q_TMP_CRY(14),
COUT => Q_TMP_CRY(16),
S0 => Q_TMP_S(15),
S1 => Q_TMP_S(16));
\Q_TMP_CRY_0[13]\: CCU2B
generic map(
INIT0 => "0xe400",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => GND,
C0 => Q_TMP(13),
D0 => VCC,
A1 => LD_C,
B1 => GND,
C1 => Q_TMP(14),
D1 => VCC,
CIN => Q_TMP_CRY(12),
COUT => Q_TMP_CRY(14),
S0 => Q_TMP_S(13),
S1 => Q_TMP_S(14));
\Q_TMP_CRY_0[11]\: CCU2B
generic map(
INIT0 => "0xe400",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => GND,
C0 => Q_TMP(11),
D0 => VCC,
A1 => LD_C,
B1 => GND,
C1 => Q_TMP(12),
D1 => VCC,
CIN => Q_TMP_CRY(10),
COUT => Q_TMP_CRY(12),
S0 => Q_TMP_S(11),
S1 => Q_TMP_S(12));
\Q_TMP_CRY_0[9]\: CCU2B
generic map(
INIT0 => "0xe400",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => GND,
C0 => Q_TMP(9),
D0 => VCC,
A1 => LD_C,
B1 => GND,
C1 => Q_TMP(10),
D1 => VCC,
CIN => Q_TMP_CRY(8),
COUT => Q_TMP_CRY(10),
S0 => Q_TMP_S(9),
S1 => Q_TMP_S(10));
\Q_TMP_CRY_0[7]\: CCU2B
generic map(
INIT0 => "0xe400",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => GND,
C0 => Q_TMP(7),
D0 => VCC,
A1 => LD_C,
B1 => GND,
C1 => Q_TMP(8),
D1 => VCC,
CIN => Q_TMP_CRY(6),
COUT => Q_TMP_CRY(8),
S0 => Q_TMP_S(7),
S1 => Q_TMP_S(8));
\Q_TMP_CRY_0[5]\: CCU2B
generic map(
INIT0 => "0xe400",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => GND,
C0 => Q_TMP(5),
D0 => VCC,
A1 => LD_C,
B1 => GND,
C1 => Q_TMP(6),
D1 => VCC,
CIN => Q_TMP_CRY(4),
COUT => Q_TMP_CRY(6),
S0 => Q_TMP_S(5),
S1 => Q_TMP_S(6));
\Q_TMP_CRY_0[3]\: CCU2B
generic map(
INIT0 => "0xe400",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => GND,
C0 => Q_TMP(3),
D0 => VCC,
A1 => LD_C,
B1 => GND,
C1 => Q_TMP(4),
D1 => VCC,
CIN => Q_TMP_CRY(2),
COUT => Q_TMP_CRY(4),
S0 => Q_TMP_S(3),
S1 => Q_TMP_S(4));
\Q_TMP_CRY_0[1]\: CCU2B
generic map(
INIT0 => "0xe400",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => LD_C,
B0 => GND,
C0 => Q_TMP(1),
D0 => VCC,
A1 => LD_C,
B1 => GND,
C1 => Q_TMP(2),
D1 => VCC,
CIN => Q_TMP_CRY(0),
COUT => Q_TMP_CRY(2),
S0 => Q_TMP_S(1),
S1 => Q_TMP_S(2));
\Q_TMP_CRY_0[0]\: CCU2B
generic map(
INIT0 => "0x0a0c",
INIT1 => "0xe400",
INJECT1_0 => "NO",
INJECT1_1 => "NO"
)
port map (
A0 => GND,
B0 => LD_C,
C0 => GND,
D0 => VCC,
A1 => LD_C,
B1 => GND,
C1 => Q_TMP(0),
D1 => VCC,
CIN => GND,
COUT => Q_TMP_CRY(0),
S0 => Q_TMP_CRY_0_S0(0),
S1 => Q_TMP_S(0));
NN_1 <= '0';
NN_2 <= '1';
end beh;
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