multi_top.vhm

lattice xp2 系列开发板带源码

--
-- Written by Synplicity
-- Product Version "Version 9.0L1"
-- Program "Synplify", Mapper "9.0.0, Build 139R"
-- Tue Jan 15 11:47:32 2008
--

--
-- Written by Synplify version 9.0.0, Build 139R
-- Tue Jan 15 11:47:32 2008
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library xp2;
use xp2.components.all;

entity Multi_top is
port(
  clk :  in std_logic;
  rstn :  in std_logic;
  Multi_out : out std_logic_vector(19 downto 0);
  ld :  in std_logic;
  d : in std_logic_vector(7 downto 0);
  q : out std_logic_vector(7 downto 0);
  sel_out : out std_logic_vector(3 downto 0);
  seg_data_out : out std_logic_vector(7 downto 0);
  mii_txen :  out std_logic;
  mii_rx_er :  in std_logic;
  mii_tx_er :  out std_logic;
  phya : out std_logic_vector(4 downto 0));
end Multi_top;

architecture beh of Multi_top is
  signal Q_TMP : std_logic_vector(27 downto 0);
  signal SEG_DATA_19 : std_logic_vector(7 downto 0);
  signal SEG_DATA : std_logic_vector(7 downto 0);
  signal SEG_DATA_19_0_S : std_logic_vector(3 downto 0);
  signal SEG_DATA_19_0_D : std_logic_vector(4 downto 1);
  signal Q_TMP_CRY : std_logic_vector(26 downto 0);
  signal Q_TMP_S : std_logic_vector(27 downto 0);
  signal Q_TMP_CRY_0_S0 : std_logic_vector(0 to 0);
  signal Q_TMP_S_0_S1 : std_logic_vector(27 to 27);
  signal Q_TMP_S_0_COUT : std_logic_vector(27 to 27);
  signal SEG_DATA_19_0_AM : std_logic_vector(6 downto 0);
  signal SEG_DATA_19_0_BM : std_logic_vector(6 downto 0);
  signal D_C : std_logic_vector(7 downto 0);
  signal Q_C : std_logic_vector(7 downto 0);
  signal Q_TMP_QN : std_logic_vector(27 downto 0);
  signal Q_TMP_S_I : std_logic_vector(27 downto 20);
  signal \SEG_DATA_18_7_0_.N_2\ : std_logic ;
  signal \SEG_DATA_18_7_0_.N_4\ : std_logic ;
  signal \SEG_DATA_18_7_0_.N_9\ : std_logic ;
  signal \SEG_DATA_18_7_0_.N_11\ : std_logic ;
  signal \SEG_DATA_18_7_0_.N_16\ : std_logic ;
  signal \SEG_DATA_18_7_0_.N_17\ : std_logic ;
  signal \SEG_DATA_18_7_0_.N_18\ : std_logic ;
  signal \SEG_DATA_18_7_0_.N_20\ : std_logic ;
  signal \SEG_DATA_18_7_0_.N_15\ : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal CLK_C : std_logic ;
  signal RSTN_C : std_logic ;
  signal LD_C : std_logic ;
  signal MII_RX_ER_C : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  PUR_INST: PUR port map (
      PUR => VCC);
  VCC_0: VHI port map (
      Z => VCC);
  GND_0: VLO port map (
      Z => GND);
  \Q_TMP_S_I[20]_Z253\: INV port map (
      A => Q_TMP_S(20),
      Z => Q_TMP_S_I(20));
  \Q_TMP_S_I[21]_Z254\: INV port map (
      A => Q_TMP_S(21),
      Z => Q_TMP_S_I(21));
  \Q_TMP_S_I[22]_Z255\: INV port map (
      A => Q_TMP_S(22),
      Z => Q_TMP_S_I(22));
  \Q_TMP_S_I[23]_Z256\: INV port map (
      A => Q_TMP_S(23),
      Z => Q_TMP_S_I(23));
  \Q_TMP_S_I[24]_Z257\: INV port map (
      A => Q_TMP_S(24),
      Z => Q_TMP_S_I(24));
  \Q_TMP_S_I[25]_Z258\: INV port map (
      A => Q_TMP_S(25),
      Z => Q_TMP_S_I(25));
  \Q_TMP_S_I[26]_Z259\: INV port map (
      A => Q_TMP_S(26),
      Z => Q_TMP_S_I(26));
  \Q_TMP_S_I[27]_Z260\: INV port map (
      A => Q_TMP_S(27),
      Z => Q_TMP_S_I(27));
  \SEG_DATA_0IO[0]_REG\: OFS1P3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => SEG_DATA_19(0),
    SP => RSTN_C,
    SCLK => CLK_C,
    CD => GND,
    Q => SEG_DATA(0));
  \SEG_DATA_0IO[1]_REG\: OFS1P3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => SEG_DATA_19(1),
    SP => RSTN_C,
    SCLK => CLK_C,
    CD => GND,
    Q => SEG_DATA(1));
  \SEG_DATA_0IO[2]_REG\: OFS1P3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => SEG_DATA_19(2),
    SP => RSTN_C,
    SCLK => CLK_C,
    CD => GND,
    Q => SEG_DATA(2));
  \SEG_DATA_0IO[3]_REG\: OFS1P3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => SEG_DATA_19(3),
    SP => RSTN_C,
    SCLK => CLK_C,
    CD => GND,
    Q => SEG_DATA(3));
  \SEG_DATA_0IO[4]_REG\: OFS1P3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => SEG_DATA_19(4),
    SP => RSTN_C,
    SCLK => CLK_C,
    CD => GND,
    Q => SEG_DATA(4));
  \SEG_DATA_0IO[5]_REG\: OFS1P3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => SEG_DATA_19(5),
    SP => RSTN_C,
    SCLK => CLK_C,
    CD => GND,
    Q => SEG_DATA(5));
  \SEG_DATA_0IO[6]_REG\: OFS1P3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => SEG_DATA_19(6),
    SP => RSTN_C,
    SCLK => CLK_C,
    CD => GND,
    Q => SEG_DATA(6));
  \SEG_DATA_0IO[7]_REG\: OFS1P3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => SEG_DATA_19(7),
    SP => RSTN_C,
    SCLK => CLK_C,
    CD => GND,
    Q => SEG_DATA(7));
  \Q_TMP_REP0_I_0IO[20]_REG\: OFS1P3BX port map (
      D => Q_TMP_S_I(20),
      SP => VCC,
      SCLK => CLK_C,
      PD => GND,
      Q => Q_C(0));
  \Q_TMP_REP0_I_0IO[21]_REG\: OFS1P3BX port map (
      D => Q_TMP_S_I(21),
      SP => VCC,
      SCLK => CLK_C,
      PD => GND,
      Q => Q_C(1));
  \Q_TMP_REP0_I_0IO[22]_REG\: OFS1P3BX port map (
      D => Q_TMP_S_I(22),
      SP => VCC,
      SCLK => CLK_C,
      PD => GND,
      Q => Q_C(2));
  \Q_TMP_REP0_I_0IO[23]_REG\: OFS1P3BX port map (
      D => Q_TMP_S_I(23),
      SP => VCC,
      SCLK => CLK_C,
      PD => GND,
      Q => Q_C(3));
  \Q_TMP_REP0_I_0IO[24]_REG\: OFS1P3BX port map (
      D => Q_TMP_S_I(24),
      SP => VCC,
      SCLK => CLK_C,
      PD => GND,
      Q => Q_C(4));
  \Q_TMP_REP0_I_0IO[25]_REG\: OFS1P3BX port map (
      D => Q_TMP_S_I(25),
      SP => VCC,
      SCLK => CLK_C,
      PD => GND,
      Q => Q_C(5));
  \Q_TMP_REP0_I_0IO[26]_REG\: OFS1P3BX port map (
      D => Q_TMP_S_I(26),
      SP => VCC,
      SCLK => CLK_C,
      PD => GND,
      Q => Q_C(6));
  \Q_TMP_REP0_I_0IO[27]_REG\: OFS1P3BX port map (
      D => Q_TMP_S_I(27),
      SP => VCC,
      SCLK => CLK_C,
      PD => GND,
      Q => Q_C(7));
  \Q_TMP[0]_REG\: FD1S3AX port map (
      D => Q_TMP_S(0),
      CK => CLK_C,
      Q => Q_TMP(0));
  \Q_TMP[1]_REG\: FD1S3AX port map (
      D => Q_TMP_S(1),
      CK => CLK_C,
      Q => Q_TMP(1));
  \Q_TMP[2]_REG\: FD1S3AX port map (
      D => Q_TMP_S(2),
      CK => CLK_C,
      Q => Q_TMP(2));
  \Q_TMP[3]_REG\: FD1S3AX port map (
      D => Q_TMP_S(3),
      CK => CLK_C,
      Q => Q_TMP(3));
  \Q_TMP[4]_REG\: FD1S3AX port map (
      D => Q_TMP_S(4),
      CK => CLK_C,
      Q => Q_TMP(4));
  \Q_TMP[5]_REG\: FD1S3AX port map (
      D => Q_TMP_S(5),
      CK => CLK_C,
      Q => Q_TMP(5));
  \Q_TMP[6]_REG\: FD1S3AX port map (
      D => Q_TMP_S(6),
      CK => CLK_C,
      Q => Q_TMP(6));
  \Q_TMP[7]_REG\: FD1S3AX port map (
      D => Q_TMP_S(7),
      CK => CLK_C,
      Q => Q_TMP(7));
  \Q_TMP[8]_REG\: FD1S3AX port map (
      D => Q_TMP_S(8),
      CK => CLK_C,
      Q => Q_TMP(8));
  \Q_TMP[9]_REG\: FD1S3AX port map (
      D => Q_TMP_S(9),
      CK => CLK_C,
      Q => Q_TMP(9));
  \Q_TMP[10]_REG\: FD1S3AX port map (
      D => Q_TMP_S(10),
      CK => CLK_C,
      Q => Q_TMP(10));
  \Q_TMP[11]_REG\: FD1S3AX port map (
      D => Q_TMP_S(11),
      CK => CLK_C,
      Q => Q_TMP(11));
  \Q_TMP[12]_REG\: FD1S3AX port map (
      D => Q_TMP_S(12),
      CK => CLK_C,
      Q => Q_TMP(12));
  \Q_TMP[13]_REG\: FD1S3AX port map (
      D => Q_TMP_S(13),
      CK => CLK_C,
      Q => Q_TMP(13));
  \Q_TMP[14]_REG\: FD1S3AX port map (
      D => Q_TMP_S(14),
      CK => CLK_C,
      Q => Q_TMP(14));
  \Q_TMP[15]_REG\: FD1S3AX port map (
      D => Q_TMP_S(15),
      CK => CLK_C,
      Q => Q_TMP(15));
  \Q_TMP[16]_REG\: FD1S3AX port map (
      D => Q_TMP_S(16),
      CK => CLK_C,
      Q => Q_TMP(16));
  \Q_TMP[17]_REG\: FD1S3AX port map (
      D => Q_TMP_S(17),
      CK => CLK_C,
      Q => Q_TMP(17));
  \Q_TMP[18]_REG\: FD1S3AX port map (
      D => Q_TMP_S(18),
      CK => CLK_C,
      Q => Q_TMP(18));
  \Q_TMP[19]_REG\: FD1S3AX port map (
      D => Q_TMP_S(19),
      CK => CLK_C,
      Q => Q_TMP(19));
  \Q_TMP[20]_REG\: FD1S3AX port map (
      D => Q_TMP_S(20),
      CK => CLK_C,
      Q => Q_TMP(20));
  \Q_TMP[21]_REG\: FD1S3AX port map (
      D => Q_TMP_S(21),
      CK => CLK_C,
      Q => Q_TMP(21));
  \Q_TMP[22]_REG\: FD1S3AX port map (
      D => Q_TMP_S(22),
      CK => CLK_C,
      Q => Q_TMP(22));
  \Q_TMP[23]_REG\: FD1S3AX port map (
      D => Q_TMP_S(23),
      CK => CLK_C,
      Q => Q_TMP(23));
  \Q_TMP[24]_REG\: FD1S3AX port map (
      D => Q_TMP_S(24),
      CK => CLK_C,
      Q => Q_TMP(24));
  \Q_TMP[25]_REG\: FD1S3AX port map (
      D => Q_TMP_S(25),
      CK => CLK_C,
      Q => Q_TMP(25));
  \Q_TMP[26]_REG\: FD1S3AX port map (
      D => Q_TMP_S(26),
      CK => CLK_C,
      Q => Q_TMP(26));
  \Q_TMP[27]_REG\: FD1S3AX port map (
      D => Q_TMP_S(27),
      CK => CLK_C,
      Q => Q_TMP(27));
  GSR_INST: GSR port map (
      GSR => RSTN_C);
  \PHYA_PAD[4]\: OB port map (
      I => GND,
      O => phya(4));
  \PHYA_PAD[3]\: OB port map (
      I => GND,
      O => phya(3));
  \PHYA_PAD[2]\: OB port map (
      I => GND,
      O => phya(2));
  \PHYA_PAD[1]\: OB port map (
      I => GND,
      O => phya(1));
  \PHYA_PAD[0]\: OB port map (
      I => VCC,
      O => phya(0));
  MII_TX_ER_PAD: OB port map (
      I => MII_RX_ER_C,
      O => mii_tx_er);
  MII_RX_ER_PAD: IB port map (
      I => mii_rx_er,
      O => MII_RX_ER_C);
  MII_TXEN_PAD: OB port map (
      I => VCC,
      O => mii_txen);
  \SEG_DATA_OUT_PAD[7]\: OB port map (
      I => SEG_DATA(7),
      O => seg_data_out(7));
  \SEG_DATA_OUT_PAD[6]\: OB port map (
      I => SEG_DATA(6),
      O => seg_data_out(6));
  \SEG_DATA_OUT_PAD[5]\: OB port map (
      I => SEG_DATA(5),
      O => seg_data_out(5));
  \SEG_DATA_OUT_PAD[4]\: OB port map (
      I => SEG_DATA(4),
      O => seg_data_out(4));
  \SEG_DATA_OUT_PAD[3]\: OB port map (
      I => SEG_DATA(3),
      O => seg_data_out(3));
  \SEG_DATA_OUT_PAD[2]\: OB port map (
      I => SEG_DATA(2),
      O => seg_data_out(2));
  \SEG_DATA_OUT_PAD[1]\: OB port map (
      I => SEG_DATA(1),
      O => seg_data_out(1));
  \SEG_DATA_OUT_PAD[0]\: OB port map (
      I => SEG_DATA(0),
      O => seg_data_out(0));
  \SEL_OUT_PAD[3]\: OB port map (
      I => VCC,
      O => sel_out(3));
  \SEL_OUT_PAD[2]\: OB port map (
      I => VCC,
      O => sel_out(2));
  \SEL_OUT_PAD[1]\: OB port map (
      I => VCC,
      O => sel_out(1));
  \SEL_OUT_PAD[0]\: OB port map (
      I => VCC,
      O => sel_out(0));
  \Q_PAD[7]\: OB port map (
      I => Q_C(7),
      O => q(7));
  \Q_PAD[6]\: OB port map (
      I => Q_C(6),
      O => q(6));
  \Q_PAD[5]\: OB port map (
      I => Q_C(5),
      O => q(5));
  \Q_PAD[4]\: OB port map (
      I => Q_C(4),
      O => q(4));
  \Q_PAD[3]\: OB port map (
      I => Q_C(3),
      O => q(3));
  \Q_PAD[2]\: OB port map (
      I => Q_C(2),
      O => q(2));
  \Q_PAD[1]\: OB port map (
      I => Q_C(1),
      O => q(1));
  \Q_PAD[0]\: OB port map (
      I => Q_C(0),
      O => q(0));
  \D_PAD[7]\: IB port map (
      I => d(7),
      O => D_C(7));
  \D_PAD[6]\: IB port map (
      I => d(6),
      O => D_C(6));
  \D_PAD[5]\: IB port map (
      I => d(5),
      O => D_C(5));
  \D_PAD[4]\: IB port map (
      I => d(4),
      O => D_C(4));
  \D_PAD[3]\: IB port map (
      I => d(3),
      O => D_C(3));
  \D_PAD[2]\: IB port map (
      I => d(2),
      O => D_C(2));
  \D_PAD[1]\: IB port map (
      I => d(1),
      O => D_C(1));
  \D_PAD[0]\: IB port map (
      I => d(0),
      O => D_C(0));