data_multi.vhd

lattice xp2 系列开发板带源码

-- VHDL netlist generated by SCUBA ispLever_v70_SP1_Build (25)
-- Module  Version: 2.3
--E:\ispTOOLS7_0\ispfpga\bin\nt\scuba.exe -w -n Data_multi -lang vhdl -synth synplify -bus_exp 7 -bb -arch mg5a00 -type dspmult -widtha 16 -widthb 4 -widthp 20 -gsr DISABLED -area -regp -regpclk CLK0 -regprst RST0 -clk0 -rst0 -e 

-- Mon Nov 12 11:34:01 2007

library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library xp2;
use xp2.components.all;
-- synopsys translate_on

entity Data_multi is
    port (
        CLK0: in  std_logic; 
        RST0: in  std_logic; 
        A: in  std_logic_vector(15 downto 0); 
        B: in  std_logic_vector(3 downto 0); 
        P: out  std_logic_vector(19 downto 0));
end Data_multi;

architecture Structure of Data_multi is

    -- internal signal declarations
    signal scuba_vhi: std_logic;
    signal scuba_vlo: std_logic;

    -- local component declarations
    component VHI
        port (Z: out  std_logic);
    end component;
    component VLO
        port (Z: out  std_logic);
    end component;
    component MULT18X18B
    -- synopsys translate_off
        generic (GSR : in String; REG_SIGNEDB_RST : in String; 
                REG_SIGNEDB_CE : in String; REG_SIGNEDB_CLK : in String; 
                REG_SIGNEDA_RST : in String; REG_SIGNEDA_CE : in String; 
                REG_SIGNEDA_CLK : in String; REG_OUTPUT_RST : in String; 
                REG_OUTPUT_CE : in String; REG_OUTPUT_CLK : in String; 
                REG_PIPELINE_RST : in String; 
                REG_PIPELINE_CE : in String; 
                REG_PIPELINE_CLK : in String; REG_INPUTB_RST : in String; 
                REG_INPUTB_CE : in String; REG_INPUTB_CLK : in String; 
                REG_INPUTA_RST : in String; REG_INPUTA_CE : in String; 
                REG_INPUTA_CLK : in String);
    -- synopsys translate_on
        port (A17: in  std_logic; A16: in  std_logic; A15: in  std_logic; 
            A14: in  std_logic; A13: in  std_logic; A12: in  std_logic; 
            A11: in  std_logic; A10: in  std_logic; A9: in  std_logic; 
            A8: in  std_logic; A7: in  std_logic; A6: in  std_logic; 
            A5: in  std_logic; A4: in  std_logic; A3: in  std_logic; 
            A2: in  std_logic; A1: in  std_logic; A0: in  std_logic; 
            B17: in  std_logic; B16: in  std_logic; B15: in  std_logic; 
            B14: in  std_logic; B13: in  std_logic; B12: in  std_logic; 
            B11: in  std_logic; B10: in  std_logic; B9: in  std_logic; 
            B8: in  std_logic; B7: in  std_logic; B6: in  std_logic; 
            B5: in  std_logic; B4: in  std_logic; B3: in  std_logic; 
            B2: in  std_logic; B1: in  std_logic; B0: in  std_logic; 
            SIGNEDA: in  std_logic; SIGNEDB: in  std_logic; 
            SOURCEA: in  std_logic; SOURCEB: in  std_logic; 
            CE0: in  std_logic; CE1: in  std_logic; CE2: in  std_logic; 
            CE3: in  std_logic; CLK0: in  std_logic; CLK1: in  std_logic; 
            CLK2: in  std_logic; CLK3: in  std_logic; 
            RST0: in  std_logic; RST1: in  std_logic; 
            RST2: in  std_logic; RST3: in  std_logic; 
            SRIA17: in  std_logic; SRIA16: in  std_logic; 
            SRIA15: in  std_logic; SRIA14: in  std_logic; 
            SRIA13: in  std_logic; SRIA12: in  std_logic; 
            SRIA11: in  std_logic; SRIA10: in  std_logic; 
            SRIA9: in  std_logic; SRIA8: in  std_logic; 
            SRIA7: in  std_logic; SRIA6: in  std_logic; 
            SRIA5: in  std_logic; SRIA4: in  std_logic; 
            SRIA3: in  std_logic; SRIA2: in  std_logic; 
            SRIA1: in  std_logic; SRIA0: in  std_logic; 
            SRIB17: in  std_logic; SRIB16: in  std_logic; 
            SRIB15: in  std_logic; SRIB14: in  std_logic; 
            SRIB13: in  std_logic; SRIB12: in  std_logic; 
            SRIB11: in  std_logic; SRIB10: in  std_logic; 
            SRIB9: in  std_logic; SRIB8: in  std_logic; 
            SRIB7: in  std_logic; SRIB6: in  std_logic; 
            SRIB5: in  std_logic; SRIB4: in  std_logic; 
            SRIB3: in  std_logic; SRIB2: in  std_logic; 
            SRIB1: in  std_logic; SRIB0: in  std_logic; 
            SROA17: out  std_logic; SROA16: out  std_logic; 
            SROA15: out  std_logic; SROA14: out  std_logic; 
            SROA13: out  std_logic; SROA12: out  std_logic; 
            SROA11: out  std_logic; SROA10: out  std_logic; 
            SROA9: out  std_logic; SROA8: out  std_logic; 
            SROA7: out  std_logic; SROA6: out  std_logic; 
            SROA5: out  std_logic; SROA4: out  std_logic; 
            SROA3: out  std_logic; SROA2: out  std_logic; 
            SROA1: out  std_logic; SROA0: out  std_logic; 
            SROB17: out  std_logic; SROB16: out  std_logic; 
            SROB15: out  std_logic; SROB14: out  std_logic; 
            SROB13: out  std_logic; SROB12: out  std_logic; 
            SROB11: out  std_logic; SROB10: out  std_logic; 
            SROB9: out  std_logic; SROB8: out  std_logic; 
            SROB7: out  std_logic; SROB6: out  std_logic; 
            SROB5: out  std_logic; SROB4: out  std_logic; 
            SROB3: out  std_logic; SROB2: out  std_logic; 
            SROB1: out  std_logic; SROB0: out  std_logic; 
            P35: out  std_logic; P34: out  std_logic; 
            P33: out  std_logic; P32: out  std_logic; 
            P31: out  std_logic; P30: out  std_logic; 
            P29: out  std_logic; P28: out  std_logic; 
            P27: out  std_logic; P26: out  std_logic; 
            P25: out  std_logic; P24: out  std_logic; 
            P23: out  std_logic; P22: out  std_logic; 
            P21: out  std_logic; P20: out  std_logic; 
            P19: out  std_logic; P18: out  std_logic; 
            P17: out  std_logic; P16: out  std_logic; 
            P15: out  std_logic; P14: out  std_logic; 
            P13: out  std_logic; P12: out  std_logic; 
            P11: out  std_logic; P10: out  std_logic; P9: out  std_logic; 
            P8: out  std_logic; P7: out  std_logic; P6: out  std_logic; 
            P5: out  std_logic; P4: out  std_logic; P3: out  std_logic; 
            P2: out  std_logic; P1: out  std_logic; P0: out  std_logic);
    end component;
    attribute GSR : string; 
    attribute REG_SIGNEDB_RST : string; 
    attribute REG_SIGNEDB_CE : string; 
    attribute REG_SIGNEDB_CLK : string; 
    attribute REG_SIGNEDA_RST : string; 
    attribute REG_SIGNEDA_CE : string; 
    attribute REG_SIGNEDA_CLK : string; 
    attribute REG_OUTPUT_RST : string; 
    attribute REG_OUTPUT_CE : string; 
    attribute REG_OUTPUT_CLK : string; 
    attribute REG_PIPELINE_RST : string; 
    attribute REG_PIPELINE_CE : string; 
    attribute REG_PIPELINE_CLK : string; 
    attribute REG_INPUTB_RST : string; 
    attribute REG_INPUTB_CE : string; 
    attribute REG_INPUTB_CLK : string; 
    attribute REG_INPUTA_RST : string; 
    attribute REG_INPUTA_CE : string; 
    attribute REG_INPUTA_CLK : string; 
    attribute GSR of dsp_0 : label is "ENABLED";
    attribute REG_SIGNEDB_RST of dsp_0 : label is "RST0";
    attribute REG_SIGNEDB_CE of dsp_0 : label is "CE0";
    attribute REG_SIGNEDB_CLK of dsp_0 : label is "NONE";
    attribute REG_SIGNEDA_RST of dsp_0 : label is "RST0";
    attribute REG_SIGNEDA_CE of dsp_0 : label is "CE0";
    attribute REG_SIGNEDA_CLK of dsp_0 : label is "NONE";
    attribute REG_OUTPUT_RST of dsp_0 : label is "RST0";
    attribute REG_OUTPUT_CE of dsp_0 : label is "CE0";
    attribute REG_OUTPUT_CLK of dsp_0 : label is "NONE";
    attribute REG_PIPELINE_RST of dsp_0 : label is "RST0";
    attribute REG_PIPELINE_CE of dsp_0 : label is "CE0";
    attribute REG_PIPELINE_CLK of dsp_0 : label is "CLK0";
    attribute REG_INPUTB_RST of dsp_0 : label is "RST0";
    attribute REG_INPUTB_CE of dsp_0 : label is "CE0";
    attribute REG_INPUTB_CLK of dsp_0 : label is "NONE";
    attribute REG_INPUTA_RST of dsp_0 : label is "RST0";
    attribute REG_INPUTA_CE of dsp_0 : label is "CE0";
    attribute REG_INPUTA_CLK of dsp_0 : label is "NONE";

begin
    -- component instantiation statements
    scuba_vhi_inst: VHI
        port map (Z=>scuba_vhi);

    scuba_vlo_inst: VLO
        port map (Z=>scuba_vlo);

    dsp_0: MULT18X18B
        -- synopsys translate_off
        generic map (GSR=> "ENABLED", REG_SIGNEDB_RST=> "RST0", 
        REG_SIGNEDB_CE=> "CE0", REG_SIGNEDB_CLK=> "NONE", 
        REG_SIGNEDA_RST=> "RST0", REG_SIGNEDA_CE=> "CE0", 
        REG_SIGNEDA_CLK=> "NONE", REG_OUTPUT_RST=> "RST0", REG_OUTPUT_CE=> "CE0", 
        REG_OUTPUT_CLK=> "NONE", REG_PIPELINE_RST=> "RST0", 
        REG_PIPELINE_CE=> "CE0", REG_PIPELINE_CLK=> "CLK0", 
        REG_INPUTB_RST=> "RST0", REG_INPUTB_CE=> "CE0", REG_INPUTB_CLK=> "NONE", 
        REG_INPUTA_RST=> "RST0", REG_INPUTA_CE=> "CE0", REG_INPUTA_CLK=> "NONE")
        -- synopsys translate_on
        port map (A17=>A(15), A16=>A(14), A15=>A(13), A14=>A(12), 
            A13=>A(11), A12=>A(10), A11=>A(9), A10=>A(8), A9=>A(7), 
            A8=>A(6), A7=>A(5), A6=>A(4), A5=>A(3), A4=>A(2), A3=>A(1), 
            A2=>A(0), A1=>scuba_vlo, A0=>scuba_vlo, B17=>B(3), B16=>B(2), 
            B15=>B(1), B14=>B(0), B13=>scuba_vlo, B12=>scuba_vlo, 
            B11=>scuba_vlo, B10=>scuba_vlo, B9=>scuba_vlo, B8=>scuba_vlo, 
            B7=>scuba_vlo, B6=>scuba_vlo, B5=>scuba_vlo, B4=>scuba_vlo, 
            B3=>scuba_vlo, B2=>scuba_vlo, B1=>scuba_vlo, B0=>scuba_vlo, 
            SIGNEDA=>scuba_vlo, SIGNEDB=>scuba_vlo, SOURCEA=>scuba_vlo, 
            SOURCEB=>scuba_vlo, CE0=>scuba_vhi, CE1=>scuba_vhi, 
            CE2=>scuba_vhi, CE3=>scuba_vhi, CLK0=>CLK0, CLK1=>scuba_vlo, 
            CLK2=>scuba_vlo, CLK3=>scuba_vlo, RST0=>RST0, 
            RST1=>scuba_vlo, RST2=>scuba_vlo, RST3=>scuba_vlo, 
            SRIA17=>scuba_vlo, SRIA16=>scuba_vlo, SRIA15=>scuba_vlo, 
            SRIA14=>scuba_vlo, SRIA13=>scuba_vlo, SRIA12=>scuba_vlo, 
            SRIA11=>scuba_vlo, SRIA10=>scuba_vlo, SRIA9=>scuba_vlo, 
            SRIA8=>scuba_vlo, SRIA7=>scuba_vlo, SRIA6=>scuba_vlo, 
            SRIA5=>scuba_vlo, SRIA4=>scuba_vlo, SRIA3=>scuba_vlo, 
            SRIA2=>scuba_vlo, SRIA1=>scuba_vlo, SRIA0=>scuba_vlo, 
            SRIB17=>scuba_vlo, SRIB16=>scuba_vlo, SRIB15=>scuba_vlo, 
            SRIB14=>scuba_vlo, SRIB13=>scuba_vlo, SRIB12=>scuba_vlo, 
            SRIB11=>scuba_vlo, SRIB10=>scuba_vlo, SRIB9=>scuba_vlo, 
            SRIB8=>scuba_vlo, SRIB7=>scuba_vlo, SRIB6=>scuba_vlo, 
            SRIB5=>scuba_vlo, SRIB4=>scuba_vlo, SRIB3=>scuba_vlo, 
            SRIB2=>scuba_vlo, SRIB1=>scuba_vlo, SRIB0=>scuba_vlo, 
            SROA17=>open, SROA16=>open, SROA15=>open, SROA14=>open, 
            SROA13=>open, SROA12=>open, SROA11=>open, SROA10=>open, 
            SROA9=>open, SROA8=>open, SROA7=>open, SROA6=>open, 
            SROA5=>open, SROA4=>open, SROA3=>open, SROA2=>open, 
            SROA1=>open, SROA0=>open, SROB17=>open, SROB16=>open, 
            SROB15=>open, SROB14=>open, SROB13=>open, SROB12=>open, 
            SROB11=>open, SROB10=>open, SROB9=>open, SROB8=>open, 
            SROB7=>open, SROB6=>open, SROB5=>open, SROB4=>open, 
            SROB3=>open, SROB2=>open, SROB1=>open, SROB0=>open, 
            P35=>P(19), P34=>P(18), P33=>P(17), P32=>P(16), P31=>P(15), 
            P30=>P(14), P29=>P(13), P28=>P(12), P27=>P(11), P26=>P(10), 
            P25=>P(9), P24=>P(8), P23=>P(7), P22=>P(6), P21=>P(5), 
            P20=>P(4), P19=>P(3), P18=>P(2), P17=>P(1), P16=>P(0), 
            P15=>open, P14=>open, P13=>open, P12=>open, P11=>open, 
            P10=>open, P9=>open, P8=>open, P7=>open, P6=>open, P5=>open, 
            P4=>open, P3=>open, P2=>open, P1=>open, P0=>open);

end Structure;

-- synopsys translate_off
library xp2;
configuration Structure_CON of Data_multi is
    for Structure
        for all:VHI use entity xp2.VHI(V); end for;
        for all:VLO use entity xp2.VLO(V); end for;
        for all:MULT18X18B use entity xp2.MULT18X18B(V); end for;
    end for;
end Structure_CON;

-- synopsys translate_on