clk_adj_tmpl.vhd

来自「lattice xp2 系列开发板带源码」· VHDL 代码 · 共 14 行

-- VHDL module instantiation generated by SCUBA ispLever_v70_SP1_Build (25)
-- Module  Version: 3.6
-- Mon Nov 12 11:33:15 2007

-- parameterized module component declaration
component clk_adj
    port (CLK: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; 
        LOCK: out std_logic);
end component;

-- parameterized module component instance
__ : clk_adj
    port map (CLK=>__, CLKOP=>__, CLKOS=>__, LOCK=>__);