clk_adj.lpc

来自「lattice xp2 系列开发板带源码」· LPC 代码 · 共 62 行

[Device]
Family=latticexp2
PartType=LFXP2-17E
PartName=LFXP2-17E-5Q208CES
SpeedGrade=-5
Package=PQFP208
OperatingCondition=COM
Status=P

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=PLL
CoreRevision=3.6
ModuleName=clk_adj
SourceFormat=VHDL
ParameterFileVersion=1.0
Date=11/12/2007
Time=11:33:15

[Parameters]
Verilog=0
VHDL=1
EDIF=1
Destination=Synplicity
Expression=None
Order=None
IO=0
Type=ehxpllb
mode=normal
IFrq=50
OFrq=50.000000
KFrq=
U_OFrq=50
U_KFrq=50
OP_Tol=0.0
OK_Tol=0.0
Div=1
Mult=1
Post=16
SecD=2
fb_mode=CLKOP
PhaseDuty=Static
DelayControl=No
PCDR=0
ClkOPBp=0
EnCLKOS=1
ClkOSBp=0
Phase=90.0
Duty=8
DPD=50% Duty
EnCLKOK=0
ClkOKBp=0
ClkRst=0
DutyTrimP=Rising
DelayMultP=0
DutyTrimS=Rising
DelayMultS=0
ClkOSDelay=0
enClkOK2=0