clk_adj_generate.log

lattice xp2 系列开发板带源码

Starting process: 

SCUBA, Version ispLever_v70_Prod_Build (55)
Mon Nov 12 11:33:15 2007

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights reserved.

BEGIN SCUBA Module Synthesis

    Issued command   : E:\ispTOOLS7_0\ispfpga\bin\nt\scuba.exe -w -n clk_adj -lang vhdl -synth synplify -arch mg5a00 -type pll -fin 50 -phase_cntl STATIC -fclkop 50 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 90.0 -duty 8 -noclkok -norst -noclkok2 -e 
    Circuit name     : clk_adj
    Module type      : pll
    Module Version   : 3.6
    Ports            : 
	Inputs       : CLK
	Outputs      : CLKOP, CLKOS, LOCK
    I/O buffer       : not inserted
    EDIF output      : suppressed
    VHDL output      : clk_adj.vhd
    VHDL template    : clk_adj_tmpl.vhd
    VHDL purpose     : for synthesis and simulation
    Bus notation     : not used
    Report output    : clk_adj.srp
    Estimated Resource Usage:

END   SCUBA Module Synthesis

File: clk_adj.lpc created.


End process: completed successfully.


Total Warnings:  0

Total Errors:  0