data_rom_tmpl.vhd

来自「lattice xp2 系列开发板带源码」· VHDL 代码 · 共 16 行

-- VHDL module instantiation generated by SCUBA ispLever_v70_SP1_Build (25)
-- Module  Version: 4.1
-- Mon Nov 12 11:33:50 2007

-- parameterized module component declaration
component Data_rom
    port (Address: in  std_logic_vector(3 downto 0); 
        OutClock: in  std_logic; OutClockEn: in  std_logic; 
        Reset: in  std_logic; Q: out  std_logic_vector(15 downto 0));
end component;

-- parameterized module component instance
__ : Data_rom
    port map (Address(3 downto 0)=>__, OutClock=>__, OutClockEn=>__, 
        Reset=>__, Q(15 downto 0)=>__);