multi_top.vhd.bak

lattice xp2 系列开发板带源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Multi_top is
port(
			clk: in std_logic;
			rstn: in std_logic;
			--Multi logic
			Multi_out: out std_logic_vector(19 downto 0);
			
			--Led display
			ld: in std_logic;
			d: in std_logic_vector(7 downto 0);
			q:out std_logic_vector(7 downto 0);

			sel_out:out std_logic_vector(3 downto 0);
			seg_data_out:out std_logic_vector(7 downto 0);	--[A,B,C,D,E,F,G,dot]
			
			mii_txen: out std_logic;
			mii_rx_er: in std_logic;
			mii_tx_er: out std_logic;
			phya: out std_logic_vector(4 downto 0)

			);
end;

architecture Multi_top_arch of Multi_top is
mii_tx_er<=mii_rx_er;
mii_txen<='1';
phya<="00001";

--component Data_rom
--    port (Address: in  std_logic_vector(3 downto 0); 
--        OutClock: in  std_logic; OutClockEn: in  std_logic; 
--        Reset: in  std_logic; Q: out  std_logic_vector(15 downto 0));
--end component;
--
--component Data_multi
--    port (CLK0: in  std_logic; A: in  std_logic_vector(15 downto 0); 
--    		RST0: in  std_logic; 
--        B: in  std_logic_vector(3 downto 0); 
--        P: out  std_logic_vector(19 downto 0));
--end component;

signal cnt,cnt_d0: std_logic_vector(3 downto 0);
signal qout: std_logic_vector(15 downto 0);
signal rst: std_logic;

signal q_tmp:std_logic_vector(27 downto 0);
signal seg_data: std_logic_vector(7 downto 0);


begin
rst<= not rstn;
process(clk,rstn)
begin
	if rstn='0' then
		cnt<=(others=>'0');
	elsif clk'event and clk='1' then
		cnt<=cnt+1;
		cnt_d0<=cnt;
	end if;
end process;
		
--U0_multi : Data_multi
--    port map (CLK0=>clk,
--    					RST0=>rst,
--    					A(15 downto 0)=>qout,
--    					B(3 downto 0)=>cnt_d0,
--    					P(19 downto 0)=>Multi_out);
--
--U1_Rom : Data_rom
--    port map (Address(3 downto 0)=>cnt,
--    					OutClock=>clk,
--    					OutClockEn=>'1',
--    					Reset=>rst,
--    					Q(15 downto 0)=>qout);
--    					
    					
 ----LED display logic
 
--------------------------------------
process(clk,rstn)
begin
	if rstn='0' then 
			q_tmp<=(others=>'0');
	elsif clk'event and clk='1' then
		if ld='0' then
			q_tmp(27 downto 20)<=d;
			q_tmp(19 downto 0)<=(others=>'0');
			seg_data<=d;
		else
			q_tmp<=q_tmp+1;
			case q_tmp(27 downto 24) is
				when "0000"=>
					seg_data<="11000000";	--0
				when "0001"=>
					seg_data<="01111001";	--1
				when "0010"=>
					seg_data<="10100100";	--2
				when "0011"=>
					seg_data<="00110000";	--3
				when "0100"=>
					seg_data<="10011001";	--4
				when "0101"=>
					seg_data<="00010010";	--5
				when "0110"=>
					seg_data<="10000010";	--6
				when "0111"=>
					seg_data<="01111000";	--7
				when "1000"=>
					seg_data<="10000000";	--8
				when "1001"=>
					seg_data<="00010000";	--9
				when "1010"=>
					seg_data<="10001000";	--A
				when "1011"=>
					seg_data<="00000011";	--b
				when "1100"=>
					seg_data<="11000110";	--c
				when "1101"=>
					seg_data<="00100001";	--d
				when "1110"=>
					seg_data<="10000110";	--E
				when "1111"=>
					seg_data<="00001110";	--F
				when others=>
					null;
			end case;
		end if;		
	end if;
end process;
seg_data_out<=seg_data;
sel_out<="1111";

q<=not q_tmp(27 downto 20);

end Multi_top_arch;