multi_top.tlg

lattice xp2 系列开发板带源码

@N: CD630 :"C:\temp\xp2_demo\multi_top.vhd":6:7:6:15|Synthesizing work.multi_top.multi_top_arch 
@W: CD638 :"C:\temp\xp2_demo\multi_top.vhd":45:7:45:10|Signal qout is undriven 
Post processing for work.multi_top.multi_top_arch
@W: CL240 :"C:\temp\xp2_demo\multi_top.vhd":11:3:11:11|Multi_out is not assigned a value (floating) - a simulation mismatch is possible 
@W: CL169 :"C:\temp\xp2_demo\multi_top.vhd":61:1:61:2|Pruning Register cnt_d0(3 downto 0)  
@W: CL169 :"C:\temp\xp2_demo\multi_top.vhd":61:1:61:2|Pruning Register cnt(3 downto 0)  
@W: CL112 :"C:\temp\xp2_demo\multi_top.vhd":89:1:89:2|Feedback mux created for signal seg_data[7:0]. Did you forget the set/reset assignment for this signal?