out_ctl.vhd

时钟滤波器设计

library ieee;
use ieee.std_logic_1164.all;

entity out_ctl is	
	port (dina  : in std_logic_vector(7 downto 0);  
	      sck   : in std_logic;
              f_out : buffer std_logic
            
             );
end out_ctl;

architecture out_ctl_bh of out_ctl is
begin  
process (sck)	
begin  
   if(sck'event and sck='0') then
      if(dina="11111111")then
         f_out<= '1';
      elsif(dina="00000000")then
 	 f_out<= '0';
      else 
         f_out<=f_out;
      end if;
end if;
end process;
end out_ctl_bh;