reg_shift8.vhd

时钟滤波器设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity reg_shift8 is
   port( SCK, SDI ,rst:in std_logic;
         dout : out std_logic_vector(7 downto 0));
end reg_shift8;

architecture reg_shift8_bh of reg_shift8 is
      signal shifted : std_logic_vector(7 downto 0);
begin
   process(SCK,SDI)
   begin
   if (rst  = '0') then
       shifted<="00000000";
      else
         if (rising_edge(SCK)) then
            shifted(0) <= SDI;
             for i in 1 to 7 loop
               shifted(i) <= shifted(i-1);
             end loop;

   end if;
  end if;
   dout <= shifted;
   end process;
end reg_shift8_bh;