fliter_tb.vhd

来自「时钟滤波器设计」· VHDL 代码 · 共 61 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT FILTER
	PORT(
		sck : IN std_logic;
		sdi : IN std_logic;
		rst : IN std_logic;          
		fout : OUT std_logic
		);
	END COMPONENT;

	SIGNAL sck :  std_logic;
	SIGNAL sdi :  std_logic;
	SIGNAL rst :  std_logic;
	SIGNAL fout :  std_logic;

BEGIN

	uut: FILTER PORT MAP(
		sck => sck,
		sdi => sdi,
		rst => rst,
		fout => fout
	);

-- *** Test Bench - User Defined Section ***
  process
   begin
      rst <='0'; wait for 0.5 ms;
      rst <='1'; 
      wait ;
   end process;

  process
   begin
      sck<='1'; wait for 0.5 ms;
      sck<='0'; wait for 0.5 ms; 
   end process;

    process
   begin
      sdi<='1'; wait for 16 ms;
      sdi<='0'; wait for 16 ms;
      sdi<='1'; wait for 2.6 ms;
      sdi<='0'; wait for 28.8ms; 
   end process;


end architecture behavior;