testbench.vhd

fifo vhdl源码

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT aFifo
	PORT(
		ReadEn_in : IN std_logic;
		RClk : IN std_logic;
		Data_in : IN std_logic_vector(7 downto 0);
		WriteEn_in : IN std_logic;
		WClk : IN std_logic;
		Clear_in : IN std_logic;          
		Data_out : OUT std_logic_vector(7 downto 0);
		Empty_out : OUT std_logic;
		Full_out : OUT std_logic
		);
	END COMPONENT;

	SIGNAL Data_in :  std_logic_vector(7 downto 0) := (others => '0');
	SIGNAL ReadEn_in :  std_logic := '0';
	SIGNAL RClk :  std_logic := '0';
 	SIGNAL WriteEn_in :  std_logic := '0';
	SIGNAL WClk :  std_logic := '0';
	SIGNAL Clear_in :  std_logic := '0'; 	
  SIGNAL Data_out :  std_logic_vector(7 downto 0);
	SIGNAL Empty_out :  std_logic;
	SIGNAL Full_out :  std_logic;
	
BEGIN

	uut: aFifo PORT MAP(
		Data_out => Data_out,
		Empty_out => Empty_out,
		ReadEn_in => ReadEn_in,
		RClk => RClk,
		Data_in => Data_in,
		Full_out => Full_out,
		WriteEn_in => WriteEn_in,
		WClk => WClk,
		Clear_in => Clear_in
	);

-- Data_in 
 PROCESS
   BEGIN
      Data_in <= (others => '0') ;
      wait for 100 ns;
      wait until Clear_in = '0';
      for i in 0 to 15 loop
        wait until WClk'event and WClk = '1';
        Data_in <= Data_in + '1' after 1 ns;
      end loop;
      wait;
   END PROCESS;

--RClk  WClk
    RClk <= not RClk after 5.00 ns;

    WClk <= not WClk after 5.00 ns;

-- 
 PROCESS
   BEGIN
          Clear_in <= '1' ;
      wait for 100 ns;
      Clear_in <= '0' ;
      wait;  
   END PROCESS;
    
-- 
 PROCESS
   BEGIN
       WriteEn_in <= '0' ;
       wait for 100 ns;
       wait until Clear_in = '0';
       for i in 0 to 15 loop
         wait until WClk'event and WClk = '1';
         WriteEn_in <= '1' after 1 ns;
       end loop;
       WriteEn_in <= '0' ;
       wait;
      
   END PROCESS;

-- ReadEn_in
 PROCESS
   BEGIN
        
       ReadEn_in <= '0' ;
       wait until Clear_in = '0';
       wait until WriteEn_in = '1';
       wait until WriteEn_in = '0';
       for i in 0 to 15 loop
         wait until RClk'event and RClk = '1';
         ReadEn_in <= '1' after 1 ns;
       end loop;
       ReadEn_in <= '0' ;
       wait;
    
   END PROCESS;
     
END architecture behavior;