asynram.vhd

来自「根据实验要求」· VHDL 代码 · 共 39 行

--实验10-2 RAM存储器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY asynram IS
GENERIC(ram_width: POSITIVE :=8;
        adr_width : POSITIVE :=4); --2**3 × 4位的RAM
PORT (  din  : IN  STD_LOGIC_VECTOR((ram_width-1) DOWNTO 0);
		dout : OUT STD_LOGIC_VECTOR((ram_width-1) DOWNTO 0);
		adr  : IN  STD_LOGIC_VECTOR((adr_width -1) DOWNTO 0);
		cs   : IN  STD_LOGIC;
		wr   : IN  STD_LOGIC;
		rd   : IN  STD_LOGIC
);
END asynram;

ARCHITECTURE rtl OF asynram IS
SUBTYPE ram_word IS STD_LOGIC_VECTOR(0 TO (ram_width-1) );
TYPE ram_type IS ARRAY (0 TO (2**adr_width -1)) OF ram_word;
SIGNAL ram:ram_type;
BEGIN
	PROCESS(wr) 	BEGIN
		IF wr'EVENT AND wr='1' THEN
			IF cs='0' THEN
				ram(conv_integer(adr)) <= din;
			END IF;
		END IF;
	END PROCESS;

	PROCESS(adr,cs,rd,ram)	BEGIN
		IF cs='0' AND rd ='0' THEN
			dout <= ram(conv_integer(adr));
		ELSE
			dout <= (others => 'Z');
		END IF;
	END PROCESS;
END rtl;