rom_mem.vhd

来自「根据实验要求」· VHDL 代码 · 共 53 行

--实验10-1 ROM存储器
PACKAGE rompac IS
CONSTANT rom_width : POSITIVE := 8;
CONSTANT adr_high  : POSITIVE := 16;
SUBTYPE rom_word IS bit_vector(0 TO (rom_width-1)); 
TYPE rom_table IS ARRAY(0 TO (adr_high-1)) OF rom_word;
CONSTANT rom:rom_table:=
					(	"00000001",
						"00000010",
						"00000011",
						"00000100",
						"00000101",
						"00000110",
						"00000111",
						"00001000",
						"00001001",
						"00001010",
						"00001011",
						"00001100",
						"00001101",
						"00001110",
						"00001111",
						"00010000" 
						);
END rompac;


USE work.rompac.ALL;
ENTITY rom_mem IS
PORT( clock : IN  bit;
      reset : IN  bit; 
      dout  : OUT bit_vector((rom_width-1) DOWNTO 0)
      );
END rom_mem;

ARCHITECTURE behav OF rom_mem IS

SIGNAL step:integer range 0 to (adr_high-1):=0;
BEGIN
	PROCESS(reset,clock) BEGIN
		if reset='0' then
			step <=0;
			--dout <= (others => '0');
		elsif clock'event and clock='1' then
			if step = (adr_high-1) THEN
				step <= adr_high-1;
			ELSE
				step <= step + 1;
			END IF;					
		end if;
	END PROCESS;
	dout <= rom(step);
END behav;