📄 avrnet.lss
字号:
8be: 40 e0 ldi r20, 0x00 ; 0
8c0: 60 e0 ldi r22, 0x00 ; 0
8c2: 8a e7 ldi r24, 0x7A ; 122
8c4: 0e 94 b9 03 call 0x772 ; 0x772 <enc28j60WriteOp>
CSACTIVE;
8c8: c4 98 cbi 0x18, 4 ; 24
// issue write command
SPDR = ENC28J60_WRITE_BUF_MEM;
8ca: 8a e7 ldi r24, 0x7A ; 122
8cc: 8f b9 out 0x0f, r24 ; 15
waitspi();
8ce: 77 99 sbic 0x0e, 7 ; 14
8d0: 09 c0 rjmp .+18 ; 0x8e4 <enc28j60_packet_send+0x60>
8d2: fd cf rjmp .-6 ; 0x8ce <enc28j60_packet_send+0x4a>
while(length)
{
length--;
8d4: 21 97 sbiw r28, 0x01 ; 1
// write data
SPDR = *buffer++;
8d6: f8 01 movw r30, r16
8d8: 80 81 ld r24, Z
8da: 8f b9 out 0x0f, r24 ; 15
waitspi();
8dc: 77 9b sbis 0x0e, 7 ; 14
8de: fe cf rjmp .-4 ; 0x8dc <enc28j60_packet_send+0x58>
8e0: 0f 5f subi r16, 0xFF ; 255
8e2: 1f 4f sbci r17, 0xFF ; 255
8e4: 20 97 sbiw r28, 0x00 ; 0
8e6: b1 f7 brne .-20 ; 0x8d4 <enc28j60_packet_send+0x50>
}
CSPASSIVE;
8e8: c4 9a sbi 0x18, 4 ; 24
// send the contents of the transmit buffer onto the network
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS); //将ECON1.TXRTS 位置1 开始发送。
8ea: 48 e0 ldi r20, 0x08 ; 8
8ec: 6f e1 ldi r22, 0x1F ; 31
8ee: 80 e8 ldi r24, 0x80 ; 128
8f0: 0e 94 b9 03 call 0x772 ; 0x772 <enc28j60WriteOp>
//TXRTS：发送请求位
//1 = 发送逻辑正在尝试发送数据包
//0 = 发送逻辑空闲
// Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12.
if( (enc28j60Read(EIR) & EIR_TXERIF) ) //TXERIF： 发送错误中断标志位
8f4: 8c e1 ldi r24, 0x1C ; 28
8f6: 0e 94 e8 03 call 0x7d0 ; 0x7d0 <enc28j60Read>
8fa: 81 ff sbrs r24, 1
8fc: 05 c0 rjmp .+10 ; 0x908 <enc28j60_packet_send+0x84>
//1 = 已发生发送错误中断
//0 = 未发生发送错误中断
{
enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
8fe: 48 e0 ldi r20, 0x08 ; 8
900: 6f e1 ldi r22, 0x1F ; 31
902: 80 ea ldi r24, 0xA0 ; 160
904: 0e 94 b9 03 call 0x772 ; 0x772 <enc28j60WriteOp>
908: df 91 pop r29
90a: cf 91 pop r28
90c: 1f 91 pop r17
90e: 0f 91 pop r16
910: 08 95 ret
00000912 <enc28j60_packet_receive>:
}
}
//*******************************************************************************************
//
// Function : enc28j60_mac_is_linked
// Description : return MAC link status.
//
//*******************************************************************************************
/*
BYTE enc28j60_mac_is_linked(void)
{
if ( (enc28j60_read_phyreg(PHSTAT1) & PHSTAT1_LLSTAT ) )
return 1;
else
return 0;
}
*/
//*******************************************************************************************
//
// Function : enc28j60_packet_receive
// Description : check received packet and return length of data
//
//*******************************************************************************************
//WORD data_length;
WORD enc28j60_packet_receive ( BYTE *rxtx_buffer, WORD max_length )
{
912: bf 92 push r11
914: cf 92 push r12
916: df 92 push r13
918: ef 92 push r14
91a: ff 92 push r15
91c: 0f 93 push r16
91e: 1f 93 push r17
920: cf 93 push r28
922: df 93 push r29
924: 6c 01 movw r12, r24
926: 7b 01 movw r14, r22
WORD_BYTES rx_status, data_length;
// check if a packet has been received and bufferedPKTIF： 接收数据包待处理中断标志位
//1 = 接收缓冲器包含一个或多个未处理的数据包；当PKTDEC 置1 时清零
//0 = 接收缓冲器为空
// if( !(enc28j60Read(EIR) & EIR_PKTIF) ){ //
// The above does not work. See Rev. B4 Silicon Errata point 6.
if( enc28j60Read(EPKTCNT) == 0 )
928: 89 e3 ldi r24, 0x39 ; 57
92a: 0e 94 e8 03 call 0x7d0 ; 0x7d0 <enc28j60Read>
92e: 88 23 and r24, r24
930: 19 f4 brne .+6 ; 0x938 <enc28j60_packet_receive+0x26>
932: 80 e0 ldi r24, 0x00 ; 0
934: 90 e0 ldi r25, 0x00 ; 0
936: 5a c0 rjmp .+180 ; 0x9ec <enc28j60_packet_receive+0xda>
{
return 0;
}
// Set the read pointer to the start of the received packet
enc28j60Write(ERDPTL, next_packet_ptr.bytes[0]);
938: 60 91 eb 00 lds r22, 0x00EB
93c: 80 e0 ldi r24, 0x00 ; 0
93e: 0e 94 f3 03 call 0x7e6 ; 0x7e6 <enc28j60Write>
enc28j60Write(ERDPTH, next_packet_ptr.bytes[1]);
942: 60 91 ec 00 lds r22, 0x00EC
946: 81 e0 ldi r24, 0x01 ; 1
948: 0e 94 f3 03 call 0x7e6 ; 0x7e6 <enc28j60Write>
// read the next packet pointer
next_packet_ptr.bytes[0] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
94c: 60 e0 ldi r22, 0x00 ; 0
94e: 8a e3 ldi r24, 0x3A ; 58
950: 0e 94 a6 03 call 0x74c ; 0x74c <enc28j60ReadOp>
954: 80 93 eb 00 sts 0x00EB, r24
next_packet_ptr.bytes[1] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
958: 60 e0 ldi r22, 0x00 ; 0
95a: 8a e3 ldi r24, 0x3A ; 58
95c: 0e 94 a6 03 call 0x74c ; 0x74c <enc28j60ReadOp>
960: b8 2e mov r11, r24
962: 80 93 ec 00 sts 0x00EC, r24
// read the packet length (see datasheet page 43)
data_length.bytes[0] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
966: 60 e0 ldi r22, 0x00 ; 0
968: 8a e3 ldi r24, 0x3A ; 58
96a: 0e 94 a6 03 call 0x74c ; 0x74c <enc28j60ReadOp>
96e: c8 2f mov r28, r24
data_length.bytes[1] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
970: 60 e0 ldi r22, 0x00 ; 0
972: 8a e3 ldi r24, 0x3A ; 58
974: 0e 94 a6 03 call 0x74c ; 0x74c <enc28j60ReadOp>
978: d8 2f mov r29, r24
data_length.word -=4; //remove the CRC count
97a: 24 97 sbiw r28, 0x04 ; 4
// read the receive status (see datasheet page 43)
rx_status.bytes[0] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
97c: 60 e0 ldi r22, 0x00 ; 0
97e: 8a e3 ldi r24, 0x3A ; 58
980: 0e 94 a6 03 call 0x74c ; 0x74c <enc28j60ReadOp>
984: 08 2f mov r16, r24
rx_status.bytes[1] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
986: 60 e0 ldi r22, 0x00 ; 0
988: 8a e3 ldi r24, 0x3A ; 58
98a: 0e 94 a6 03 call 0x74c ; 0x74c <enc28j60ReadOp>
if ( data_length.word > (max_length-1) )
98e: b7 01 movw r22, r14
990: 61 50 subi r22, 0x01 ; 1
992: 70 40 sbci r23, 0x00 ; 0
994: 6c 17 cp r22, r28
996: 7d 07 cpc r23, r29
998: 08 f4 brcc .+2 ; 0x99c <enc28j60_packet_receive+0x8a>
{
data_length.word = max_length-1;
99a: eb 01 movw r28, r22
}
// check CRC and symbol errors (see datasheet page 44, table 7-3):
// The ERXFCON.CRCEN is set by default. Normally we should not
// need to check this.
if ( (rx_status.word & 0x80)==0 )
99c: 07 fd sbrc r16, 7
99e: 03 c0 rjmp .+6 ; 0x9a6 <enc28j60_packet_receive+0x94>
{
// invalid
data_length.word = 0;
9a0: c0 e0 ldi r28, 0x00 ; 0
9a2: d0 e0 ldi r29, 0x00 ; 0
9a4: 14 c0 rjmp .+40 ; 0x9ce <enc28j60_packet_receive+0xbc>
}
else
{
// read data from rx buffer and save to rxtx_buffer
rx_status.word = data_length.word;
9a6: 9e 01 movw r18, r28
CSACTIVE;
9a8: c4 98 cbi 0x18, 4 ; 24
// issue read command
SPDR = ENC28J60_READ_BUF_MEM;
9aa: 8a e3 ldi r24, 0x3A ; 58
9ac: 8f b9 out 0x0f, r24 ; 15
waitspi();
9ae: 77 99 sbic 0x0e, 7 ; 14
9b0: 0a c0 rjmp .+20 ; 0x9c6 <enc28j60_packet_receive+0xb4>
9b2: fd cf rjmp .-6 ; 0x9ae <enc28j60_packet_receive+0x9c>
while(rx_status.word)
{
rx_status.word--;
SPDR = 0x00;
9b4: 1f b8 out 0x0f, r1 ; 15
waitspi();
9b6: 77 9b sbis 0x0e, 7 ; 14
9b8: fe cf rjmp .-4 ; 0x9b6 <enc28j60_packet_receive+0xa4>
*rxtx_buffer++ = SPDR;
9ba: 8f b1 in r24, 0x0f ; 15
9bc: f6 01 movw r30, r12
9be: 81 93 st Z+, r24
9c0: 6f 01 movw r12, r30
9c2: 21 50 subi r18, 0x01 ; 1
9c4: 30 40 sbci r19, 0x00 ; 0
9c6: 21 15 cp r18, r1
9c8: 31 05 cpc r19, r1
9ca: a1 f7 brne .-24 ; 0x9b4 <enc28j60_packet_receive+0xa2>
}
CSPASSIVE;
9cc: c4 9a sbi 0x18, 4 ; 24
}
// Move the RX read pointer to the start of the next received packet
// This frees the memory we just read out
enc28j60Write(ERXRDPTL, next_packet_ptr.bytes[0]);
9ce: 60 91 eb 00 lds r22, 0x00EB
9d2: 8c e0 ldi r24, 0x0C ; 12
9d4: 0e 94 f3 03 call 0x7e6 ; 0x7e6 <enc28j60Write>
enc28j60Write(ERXRDPTH, next_packet_ptr.bytes[1]);
9d8: 6b 2d mov r22, r11
9da: 8d e0 ldi r24, 0x0D ; 13
9dc: 0e 94 f3 03 call 0x7e6 ; 0x7e6 <enc28j60Write>
// decrement the packet counter indicate we are done with this packet
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
9e0: 40 e4 ldi r20, 0x40 ; 64
9e2: 6e e1 ldi r22, 0x1E ; 30
9e4: 80 e8 ldi r24, 0x80 ; 128
9e6: 0e 94 b9 03 call 0x772 ; 0x772 <enc28j60WriteOp>
return( data_length.word );
9ea: ce 01 movw r24, r28
9ec: df 91 pop r29
9ee: cf 91 pop r28
9f0: 1f 91 pop r17
9f2: 0f 91 pop r16
9f4: ff 90 pop r15
9f6: ef 90 pop r14
9f8: df 90 pop r13
9fa: cf 90 pop r12
9fc: bf 90 pop r11
9fe: 08 95 ret
00000a00 <enc28j60_init>:
a00: ef 92 push r14
a02: ff 92 push r15
a04: 0f 93 push r16
a06: 1f 93 push r17
a08: 7c 01 movw r14, r24
a0a: 8b 9a sbi 0x11, 3 ; 17
a0c: 8a 98 cbi 0x11, 2 ; 17
a0e: 92 9a sbi 0x12, 2 ; 18
a10: 93 98 cbi 0x12, 3 ; 18
*/
void
_delay_loop_2(uint16_t __count)
{
__asm__ volatile (
a12: 80 e4 ldi r24, 0x40 ; 64
a14: 9c e9 ldi r25, 0x9C ; 156
a16: 01 97 sbiw r24, 0x01 ; 1
a18: f1 f7 brne .-4 ; 0xa16 <enc28j60_init+0x16>
a1a: 93 9a sbi 0x12, 3 ; 18
*/
void
_delay_loop_2(uint16_t __count)
{
__asm__ volatile (
a1c: 00 e0 ldi r16, 0x00 ; 0
a1e: 10 e0 ldi r17, 0x00 ; 0
a20: c8 01 movw r24, r16
a22: 01 97 sbiw r24, 0x01 ; 1
a24: f1 f7 brne .-4 ; 0xa22 <enc28j60_init+0x22>
a26: 87 b3 in r24, 0x17 ; 23
a28: 80 6b ori r24, 0xB0 ; 176
a2a: 87 bb out 0x17, r24 ; 23
a2c: c4 9a sbi 0x18, 4 ; 24
a2e: 88 b3 in r24, 0x18 ; 24
a30: 8f 75 andi r24, 0x5F ; 95
a32: 88 bb out 0x18, r24 ; 24
a34: 80 e5 ldi r24, 0x50 ; 80
a36: 8d b9 out 0x0d, r24 ; 13
a38: 70 9a sbi 0x0e, 0 ; 14
a3a: 4f ef ldi r20, 0xFF ; 255
a3c: 60 e0 ldi r22, 0x00 ; 0
a3e: 8f ef ldi r24, 0xFF ; 255
a40: 0e 94 b9 03 call 0x772 ; 0x772 <enc28j60WriteOp>
*/
void
_delay_loop_2(uint16_t __count)
{
__asm__ volatile (
a44: c8 01 movw r24, r16
a46: 01 97 sbiw r24, 0x01 ; 1
a48: f1 f7 brne .-4 ; 0xa46 <enc28j60_init+0x46>
a4a: 10 92 ec 00 sts 0x00EC, r1
a4e: 10 92 eb 00 sts 0x00EB, r1
a52: 60 e0 ldi r22, 0x00 ; 0
a54: 88 e0 ldi r24, 0x08 ; 8
a56: 0e 94 f3 03 call 0x7e6 ; 0x7e6 <enc28j60Write>
a5a: 60 e0 ldi r22, 0x00 ; 0
a5c: 89 e0 ldi r24, 0x09 ; 9
a5e: 0e 94 f3 03 call 0x7e6 ; 0x7e6 <enc28j60Write>
a62: 60 e0 ldi r22, 0x00 ; 0
a64: 8c e0 ldi r24, 0x0C ; 12
a66: 0e 94 f3 03 call 0x7e6 ; 0x7e6 <enc28j60Write>
a6a: 60 e0 ldi r22, 0x00 ; 0
a6c: 8d e0 ldi r24, 0x0D ; 13
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