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📄 at2042_inf.c.bak

📁 这个是Linux下的关于2042的程序
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			for (ii = enc_txmsg_size; ii < data_size; ii ++) {
				mux_data=*((unsigned short *)((unsigned int)fifo_reg + AT2041_MUX_FIFO));
				mux_swap= (((mux_data<<8)&0xFF00) | ((mux_data>>8)&0x00FF));
				mux_buf[MUX_WR_COUNT][ii]=mux_swap;			
			}
		}


#if 0 	/*2005-02-07 netbsd*/	
		if ((mux_buf[MUX_WR_COUNT][enc_txmsg_size+1]>>12)==0xe) {	/*MPEG_VIDEO*/
			if ((MXV%29)==0)  printk_netbsd ("\rMXV:%lu", MXV);
			MXV++;
		}
		else if ((mux_buf[MUX_WR_COUNT][enc_txmsg_size+1]>>12)==0xd) {	/*JPEG_VIDEO*/
			if ((MXJ%29)==0)  printk_netbsd ("\r\t\tMXJ:%lu", MXJ);
			MXJ++;
		}
		else if ((mux_buf[MUX_WR_COUNT][enc_txmsg_size+1]>>12)==0xc) {	/*AUDIO*/		
			if ((MXA%9)==0) printk_netbsd ("\r\t\t\t\tMXA:%lu", MXA); 
			MXA++;
		}
		else {
 			printk_netbsd ("\n\n\n[##### %04x %04x %04x %04x : %04x %04x #####]\n\n\n", 
				mux_buf[MUX_WR_COUNT][0],mux_buf[MUX_WR_COUNT][1],
				mux_buf[MUX_WR_COUNT][2],mux_buf[MUX_WR_COUNT][3],
				mux_buf[MUX_WR_COUNT][4],mux_buf[MUX_WR_COUNT][5]);
		}
#endif	

		up(&muxfifo_read_sem);

		/* TxACK command */
		*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x8003;	
		
		if ((mux_wr_cnt-mux_rd_cnt)<MAX_BUF_NUM) {
			mux_wr_cnt++;
		}
		else {
			mux_full = 1;
			/*2005-03-17 netbsd*/
			mux_wr_cnt++;
			return ;			
		}

		if (mux_wr_cnt>MAX_CNT) {
			mux_wr_cnt=(mux_wr_cnt%MAX_BUF_NUM);
			printk_netbsd ("[### RETURN mux_wr_cnt ###]\n");
		}
		
		/* acknowledge for data ready message */
		*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x8803;						
	}	
	
	/* data write to de-multiplex FIFO of the AT2041 */
	else if (tx_data == 0x9003) 
	{	
		if (DECODER_STOP)  
		{
			int kk,gg;

			for (kk = 0; kk < MAX_BUF_NUM; kk ++)
			{				
				/*Decoder clear netbsd*/
				for (gg=0;gg<demux_size_buf[kk]/2;gg++) 
				{
					demux_buf[kk][gg]=0x0000;
				}
				demux_size_buf[kk]=INIT_CNT;
			}
			demux_wr_cnt=INIT_CNT;
			demux_rd_cnt=INIT_CNT;
			printk_netbsd ("[### DECODER_STOP COMPLETE ###]\n");							
			DECODER_STOP=0;
		}
			
		DEMUX_RD_COUNT=(demux_rd_cnt%MAX_BUF_NUM);
		
		// read message from txfifo : data request(Decoding) 
		if (demux_wr_cnt <= demux_rd_cnt) {
			/* check tx fifo empty */
			if (!(*((unsigned short *)((unsigned int)fifo_reg + AT2041_STATUS_REG)) & 0x100)) {
				/* txfifo ring buffer control */
				temp = *((unsigned short *)((unsigned int)fifo_reg + AT2041_TX_FIFO));
			} 
			else {
				printk_netbsd("[at2042 : 0x9003] It can't read tx0 register\n");			
				/* TxACK command */
				//*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x8003;
			}		
				
			/* TxACK command */
			*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x8003;			
			/* acknowledge for data request message */
// pentamicro 2005.07.28		
//			*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x9003;	
			// alternative ack. for data request
			*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x9061; 
			// d0 for alternative ack : null ack
			*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x0802;
			// d1 for alternative ack
			*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x0000;
			
			return;
		}

		/* check tx fifo empty */
		if (!(*((unsigned short *)((unsigned int)fifo_reg + AT2041_STATUS_REG)) & 0x100)) {
			/* txfifo ring buffer control */
			temp = *((unsigned short *)((unsigned int)fifo_reg + AT2041_TX_FIFO));
		} 
		else {
			printk("[at2042 : 0x9003] It can't read tx1 register\n");		
			/* TxACK command */
			//*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x8003;
		}			

#if 0 	/*2005-02-02 netbsd*/	
		if ((demux_buf[DEMUX_RD_COUNT][1]>>12)==0xe) {	/*MPEG_VIDEO*/
			if ((DXV%29)==0) printk_netbsd ("\rDXV:%lu", DXV);
			DXV++;
		}
		else if ((demux_buf[DEMUX_RD_COUNT][1]>>12)==0xd) {	/*JPEG_VIDEO*/
			if ((DXJ%29)==0) printk_netbsd ("\r\t\tDXJ:%lu", DXJ);
			DXJ++;
		}
		else if ((demux_buf[DEMUX_RD_COUNT][1]>>12)==0xc) {	/*AUDIO*/		
			if ((DXA%9)==0) printk_netbsd ("\r\t\t\t\tDXA:%lu", DXA);
			DXA++;			
			if (demux_size_buf[DEMUX_RD_COUNT] != 1088) {
				printk_netbsd ("\n\n\n[### demux_size_buf : %d]\n\n\n", demux_size_buf[DEMUX_RD_COUNT]);
				demux_size_buf[DEMUX_RD_COUNT]=1088;
			}
		}
		else {
			printk_netbsd ("\n\n\n[##### %04x %04x #####]\n\n\n", 
				demux_buf[DEMUX_RD_COUNT][0], demux_buf[DEMUX_RD_COUNT][1]);
		}
#endif


		if (demux_size_buf[DEMUX_RD_COUNT]>MAX_BUF_SIZE) 
		{
			printk_netbsd ("[##### DECODER SIZE_OVER : %08d #####]\n", demux_size_buf[DEMUX_RD_COUNT]);
#ifdef 	__EXT_CODE__		/*2005-03-09 netbsd*/		
 			for (ii = 0; ii <(demux_size_buf[DEMUX_RD_COUNT]+DEC_DUMMY)/2; ii ++) {
				demux_data=ext_demux_buf[DEMUX_RD_COUNT][ii];
				demux_swap= (((demux_data<<8)&0xFF00) | ((demux_data>>8)&0x00FF));
				*((unsigned short *)((unsigned int)fifo_reg + AT2041_DEMUX_FIFO)) = demux_swap;
			}
			vfree(ext_demux_buf[DEMUX_RD_COUNT]);
#endif
		}
		else 
		{
#if 1		/*2005-04-25 netbsd*/
 			for (ii = 0; ii < (demux_size_buf[DEMUX_RD_COUNT])/2; ii ++) {
				demux_data=demux_buf[DEMUX_RD_COUNT][ii];
				demux_swap= (((demux_data<<8)&0xFF00) | ((demux_data>>8)&0x00FF));
				*((unsigned short *)((unsigned int)fifo_reg + AT2041_DEMUX_FIFO)) = demux_swap;
			}
 			for (ii = 0; ii < DEC_DUMMY2/2; ii ++) {
				*((unsigned short *)((unsigned int)fifo_reg + AT2041_DEMUX_FIFO)) = 0x0000;
 			}
#else
			if ((demux_buf[DEMUX_RD_COUNT][1]>>12)==0xd) 	/*JPEG_VIDEO*/
			{	
	 			for (ii = 0; ii < (demux_size_buf[DEMUX_RD_COUNT])/2; ii ++) {
					demux_data=demux_buf[DEMUX_RD_COUNT][ii];
					demux_swap= (((demux_data<<8)&0xFF00) | ((demux_data>>8)&0x00FF));
					*((unsigned short *)((unsigned int)fifo_reg + AT2041_DEMUX_FIFO)) = demux_swap;
				}
	 			for (ii = 0; ii < DEC_DUMMY2/2; ii ++) {
					*((unsigned short *)((unsigned int)fifo_reg + AT2041_DEMUX_FIFO)) = 0x0000;
	 			}
			}
			else {
	 			for (ii = 0; ii < (demux_size_buf[DEMUX_RD_COUNT]+DEC_DUMMY)/2; ii ++) {
					demux_data=demux_buf[DEMUX_RD_COUNT][ii];
					demux_swap= (((demux_data<<8)&0xFF00) | ((demux_data>>8)&0x00FF));
					*((unsigned short *)((unsigned int)fifo_reg + AT2041_DEMUX_FIFO)) = demux_swap;
				}
			}
#endif			
		}

		up(&demuxfifo_write_sem);

		/* TxACK command */
		*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x8003;		

		demux_rd_cnt++;

		if (demux_rd_cnt>MAX_CNT) {
			demux_rd_cnt=(demux_rd_cnt%MAX_BUF_NUM);
			printk_netbsd ("[### RETURN demux_rd_cnt ###]\n");
		}
		
		/* acknowledge for data request message */
// pentamicro 2005.07.28
//		*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x9003;		
		// alternative ack. for data request
		*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x9061; 
		// d0 for alternative ack : last ack
		*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x0801;
		// d1 for alternative ack
		*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x0000;
	}	

	else {
		/* TxACK command */
		*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0x8003;	
	}

	return ;
}


#define VERSTION_STRING		"AT2042 Version 1.3.1-4\0"

int at2041_init_module(void)
{
	volatile int ret, kk;
	volatile int gg;
		
	printk_netbsd2 ("## BWSCON : 0x%08x ##\n" , rBWSCON);	/*BWSCON : 0x48000000*/
	
	(unsigned short *)fifo_reg = (unsigned short *)ioremap(AT2042_BASE, AT2042_REMAP_SIZE);
	
	printk_netbsd ("[### AT2042 :  0x%x ==> 0x%x ###]\n", (unsigned int)fifo_reg,  (unsigned int)fifo_reg+AT2042_REMAP_SIZE);
	
	ret = register_chrdev(AT2041_MAJOR, "at2042", &at2041_fops);

	init_MUTEX_LOCKED(&muxfifo_read_sem);	
	sema_init(&demuxfifo_write_sem, MAX_BUF_NUM);	

	if (ret < 0) {
		printk_netbsd ("at2042: at2042 register failed\n");
		return ret;
	}
		
	/* mux_buf & demux_buf allocation */
	for (kk = 0; kk < MAX_BUF_NUM; kk ++){
		if (!(mux_buf[kk] = (unsigned short *) kmalloc(MAX_BUF_SIZE + (enc_txmsg_size*2), GFP_KERNEL))) {
			printk_netbsd("AT2041 : mux_buf kmalloc failed...\n");
			return -ENOMEM;
		}
		/*2005-03-09 netbsd  + DEC_DUMMY*/
		if (!(demux_buf[kk] = (unsigned short *) kmalloc(MAX_BUF_SIZE+DEC_DUMMY, GFP_KERNEL))) {
			printk_netbsd("AT2041 : demux_buf kmalloc failed...\n");
			return -ENOMEM;
		}
		if (!(size_buf[kk] = (unsigned int *) vmalloc(sizeof(unsigned int)))) {
			printk_netbsd("AT2042 : size_buf vmalloc failed...\n");
			return -ENOMEM;
		}

		/*Encoder clear netbsd*/
		for (gg=0;gg<(MAX_BUF_SIZE/2+enc_txmsg_size);gg++) {
			mux_buf[kk][gg]=0x0000;
		}
		*size_buf[kk]=INIT_CNT;

		/*Decoder clear netbsd*/
		for (gg=0;gg<(MAX_BUF_SIZE+DEC_DUMMY)/2;gg++) {
			demux_buf[kk][gg]=0x0000;
		}
		demux_size_buf[kk]=INIT_CNT;
	}

	printk_netbsd ("[### %s ###]\n", VERSTION_STRING);
	
#if 0
	//printk ("__nWAIT_REENABLE__\n");printk ("__nWAIT_REENABLE__\n");/*netbsd*/
	//rBWSCON |= (0x5<<8);
	printk ("__nWAIT_DISABLE__\n");printk ("__nWAIT_DISABLE__\n");/*netbsd*/
	rBWSCON &= ~(0x4<<8);
	printk ("__Tacc_control__\n");printk ("__Tacc_control__\n");/*netbsd*/	
	rBANKCON2 |= (0x7<<8);		/*14CLK*/
#endif
	
	/* Enable interrupts for EINT0/GPF0 */	/*netbsd*/
	printk_netbsd2 ("__INTERRUPT_AVAILABLE__\n");	/*netbsd*/
	//rEXTINT0 = 0x22222244;    // EINT[7:0]	/*AT2042 Falling Edge Triggered*/	/*netbsd*/
	rEXTINT0 = 0x22222444;    // EINT[7:0]	/*AT2042 Rising Edge Triggered*/	/*netbsd*/
	//rINTMSK &= ~0x00000001;	//Intservice MASK ==> AVAILABLE		/*netbsd*/	
	rSRCPND |= 0x00000004;	//Intservice requested /*netbsd*/	
	//rINTMSK |=0x00000004;	//Intservice MASK ==> MASKED		/*netbsd*/	
	rINTMSK &= ~0x00000004;	//Intservice MASK ==> AVAILABLE		/*netbsd*/	

	/* AT2041_IRQ = 25, Fast interrupt, No interrupt sharing */
	//printk ("0x%x : 0x%x\n", SA_INTERRUPT, SA_SHIRQ);
	//if(request_irq(IRQ_EINT2, at2041_interrupt_handle, SA_INTERRUPT, "at2042", NULL))
	//if(request_irq(IRQ_EINT2, at2041_interrupt_handle, SA_SHIRQ, "at2042", NULL)) 		
	if(request_irq(IRQ_EINT2, at2041_interrupt_handle, 0, "at2042", NULL))
	{
		printk_netbsd("at2042 : cannot register IRQ %d\n", IRQ_EINT2);
		return -EIO;
	}
	printk_netbsd ("[### AT2042 : register IRQ %d ###]\n", IRQ_EINT2);


#if	0	/*__DMA_ENABLE__*/
	DMA_TEST = *((volatile unsigned short *)((unsigned long)pt + 0x00600000));

	gpis1 = (unsigned int*) ioremap(0x40060030,4);
	*(unsigned int*)gpis1 |=0x00400000; //DMA_REQ	

	printk("CICSEL3 %08x\n",mfdcr(0x35));	
	// DMA0 SELECT2 external DMA to DMA1 channel 0
	mtdcr(DMA1S2,0x00080000);

	// DMA Status clear
	mtdcr(DMA1SR0,0xffffffff);

	// DMA Channel control
	mtdcr(DMA1CR0,/*DMACR_CE|*/DMACR_CIE|DMACR_TD /*| DMACR_PL */|DMACR_PW_HW | DMACR_DAI | DMACR_CP |DMACR_TM_HARD|DMACR_ETD|DMACR_TCE | DMACR_RES | DMACR_CP1);

	// DMA Destination Address 
	mtdcr(DMA1DA0,(unsigned int)0xA0C00000);

	// DMA Source Address 
	mtdcr(DMA1SA0,(unsigned int)AT2021BASE + 0x00200000);	

	mtdcr(UICPR, mfdcr(UICPR) | (0x80000000 >> DMA1_INT_NUM));
	
	mtdcr(UICTR, mfdcr(UICTR) & ~(0x80000000 >> DMA1_INT_NUM));

	// DMA interrupt install
	if(request_irq(DMA1_INT_NUM, at2042_dma_handle, SA_INTERRUPT, "dma", NULL)) {
		printk("AT2021 : cannot register DMA1 IRQ %d\n", DMA1_INT_NUM);
		return -1;
 	}

	mtdcr(UICER, mfdcr(UICER) | (0x80000000 >> DMA1_INT_NUM));

	mtdcr(DMA1CR0, mfdcr(DMA1CR0) | DMACR_CE);	
	mtdcr(UICTR, (mfdcr(UICTR) | 0x00000010));
	mtdcr(UICPR, (mfdcr(UICPR) | 0x00000010));
	mtdcr(UICER, (mfdcr(UICER) | 0x00000010));
#endif


#ifdef __PIP__	/*2005-01-18*/
{
		/*Rescale*/
		unsigned short id_conf;
		udelay(1000);
		id_conf = RxID(GID_DEC_VIDEO_CH, 0x00, 0x10, W_FLAG);
		*((unsigned short  *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = id_conf;
		*((unsigned short  *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 4;// 2/3 Hor scale
		*((unsigned short  *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 4;// 2/3 Ver scale
		printk_netbsd2 ("[Display Rescale]\n"); 
		/*Deocding video offset*/		
		id_conf = RxID(GID_DEC_VIDEO_CH, 0x00, 0x11, W_FLAG);
		*((unsigned short  *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = id_conf;
		*((unsigned short  *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = (0x0c);// Hor offset
		*((unsigned short  *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = (0x08);// Ver offset		
}
#else
{
		/*Rescale*/
		unsigned short id_conf;
		udelay(1000);
		id_conf = RxID(GID_DEC_VIDEO_CH, 0x00, 0x10, W_FLAG);
		*((unsigned short  *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = id_conf;
		*((unsigned short  *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0;// 1/1 Hor scale
		*((unsigned short  *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = 0;// 1/1 Ver scale
		//printf ("[Display Rescale]\n"); 
		/*Deocding video offset*/		
		id_conf = RxID(GID_DEC_VIDEO_CH, 0x00, 0x11, W_FLAG);
		*((unsigned short  *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = id_conf;
		*((unsigned short  *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = (0x00);// Hor offset
		*((unsigned short  *)((unsigned int)fifo_reg + AT2041_RX_FIFO)) = (0x00);// Ver offset	
		printk_netbsd2 ("[Display Rescale]\n"); 
}
#endif		

	return 0;
}


void at2041_cleanup_module(void)
{
	volatile int ret;
	/*2005-03-09 netbsd*/	
	volatile unsigned int ii;
	
	free_irq(IRQ_EINT2, NULL);

	ret = unregister_chrdev(AT2041_MAJOR, "at2042");
	
	if (ret < 0) {
		printk_netbsd ("at2042: at2042 unregister failed\n");
		return;
	}

	for (ii = 0; ii < MAX_BUF_NUM; ii ++) {
		kfree(mux_buf[ii]);
		kfree(demux_buf[ii]);
		vfree(size_buf[ii]);
	}

	printk_netbsd ("[### at2041_cleanup_module ###]\n");

	iounmap((void *)fifo_reg);

	return;
}


module_init(at2041_init_module);
module_exit(at2041_cleanup_module);

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