at2041_inf.c

这个是Linux下的关于2042的程序

	
	udelay(100000);
#ifdef START_STOP_ENC
	id_conf = RxID(GID_ENCODER, 0x00, 0x02, W_FLAG);	
	set_reg_st.cmd_num=1;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
	set_reg_st.value[1]=START_STOP_ENC;
	do_mw32 ( (_SET_REG_STR_ ) set_reg_st);					
#endif

	return ;
}


static  void set_enc_mode (unsigned short mode)
{
	_SET_REG_STR_ set_reg_st={0,0,{0,0,0,0,0,0}};
	unsigned short id_conf;
	unsigned short MODE=1;
	
#ifdef START_STOP_ENC
	id_conf = RxID(GID_ENCODER, 0x00, 0x03, W_FLAG);	
	set_reg_st.cmd_num=1;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
	set_reg_st.value[1]=START_STOP_ENC;	
	do_mw32 ( (_SET_REG_STR_ ) set_reg_st);				
#endif
	udelay(100000);

	if (mode<=0) {
		MODE=0;
		printk ("[ENC_MODE : VBR]\n"); 
	}
	else {
		MODE=1;
		printk ("[ENC_MODE : CBR]\n"); 
	}
	/* Rate Control Mode : CBR : VBR */
	id_conf = RxID(GID_ENC_VIDEO_CH, 0x00, 0x04, W_FLAG);		
	set_reg_st.cmd_num=1;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
	set_reg_st.value[1]=MODE;	//0:VBR  1~2:CBR	
	do_mw32 ( (_SET_REG_STR_ ) set_reg_st);				
	
	udelay(100000);
#ifdef START_STOP_ENC
	id_conf = RxID(GID_ENCODER, 0x00, 0x02, W_FLAG);	
	set_reg_st.cmd_num=1;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
	set_reg_st.value[1]=START_STOP_ENC;
	do_mw32 ( (_SET_REG_STR_ ) set_reg_st);					
#endif

	return ;
}

static void set_res (unsigned short res, unsigned short frm)
{
	_SET_REG_STR_ set_reg_st={0,0,{0,0,0,0,0,0}};
	unsigned short id_conf, clear_cnt;
	unsigned short frame_rate;
		
#ifdef START_STOP_ENC
	id_conf = RxID(GID_ENCODER, 0x00, 0x03, W_FLAG);
	set_reg_st.cmd_num=1;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
	set_reg_st.value[1]=START_STOP_ENC;
	do_mw32 ( (_SET_REG_STR_ ) set_reg_st);				
#endif	
	udelay(100000);

	if (res==RES_MODE_DI)		/*RES_MODE_DI*/
	{
		/* Input Video Format : 0x01 */
		id_conf = RxID(GID_ENC_VIDEO, 0x00, 0x01, W_FLAG);
		set_reg_st.cmd_num=4;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
		set_reg_st.value[1]=720;		// hor_size
		if (PAL_NTSC==NTSC) {
			set_reg_st.value[2] = 480;	// ver_size
			set_reg_st.value[3] = 4;		// video_input_rate 30000/10001
			set_reg_st.value[4] = 0;		// field_mode (d1=>interlaced '0')
			//printk ("[Input video Format 720, 480, 4, 0]\n"); 
		}
		else {
			set_reg_st.value[2]  = 576;	// ver_size
			set_reg_st.value[3]  = 3;	// video_input_rate 25
			set_reg_st.value[4]  = 0;	// field_mode (d1=>interlaced '0')
			//printk ("[Input video Format 720, 576, 3, 0]\n"); 		
		}
		do_mw32 ( (_SET_REG_STR_ ) set_reg_st);
		for (clear_cnt=0;clear_cnt<6;clear_cnt++) {set_reg_st.value[clear_cnt]=0;}
		
		/*Input  video scale mode*/
		id_conf = RxID(GID_ENC_VIDEO_CH, 0x00, 0x22, W_FLAG);
		set_reg_st.cmd_num=2;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
		set_reg_st.value[1] = 0;		// hor_scale 1
		set_reg_st.value[2] = 0;		// ver_scale 1
		do_mw32 ( (_SET_REG_STR_ ) set_reg_st);
		//printk ("[Input  video scale mode : 100, 100]\n"); 
		
		/*Encoding region information*/
		id_conf = RxID(GID_ENC_VIDEO_CH, 0x00, 0x23, W_FLAG);
		set_reg_st.cmd_num=4;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
		set_reg_st.value[1]  = 0;		//hor_offset	0
		set_reg_st.value[2]  = 0;		//ver_offset	0
		set_reg_st.value[3]  = (720>>4);	//hor_MB	45
		if (PAL_NTSC==NTSC)  {	/*NTSC D1*/
			set_reg_st.value[4] = (480>>4);	//ver_MB		30
			printk ("[RESOLUTION : NTSC 720x480]\n"); 
		}
		else {	/*PAL D1*/
			set_reg_st.value[4] = (576>>4);	//ver_MB		30
			printk ("[RESOLUTION : PAL 720x576]\n"); 			
		}		
		do_mw32 ( (_SET_REG_STR_ ) set_reg_st);
		for (clear_cnt=0;clear_cnt<6;clear_cnt++) {set_reg_st.value[clear_cnt]=0;}

		id_conf = RxID(GID_ENC_VIDEO_CH, 0x00, 0x24, W_FLAG);
		set_reg_st.cmd_num=2;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
		set_reg_st.value[1] = 1;		//Input frames
		set_reg_st.value[2] = 1;		//recoded frames
		do_mw32 ( (_SET_REG_STR_ ) set_reg_st);
		for (clear_cnt=0;clear_cnt<6;clear_cnt++) {set_reg_st.value[clear_cnt]=0;}

		/*Recoding frame rate control*/
		if (frm>=30) frame_rate=30;	
		else if (frm<=1) frame_rate=1;	
		else frame_rate=frm;
		printk ("[FRAME_RATE : %d/SEC]\n" , frame_rate);
		
#if 0		
		/* Zoomin */
		id_conf = RxID(GID_DEC_VIDEO, 0, 0x10, W_FLAG);	
		set_reg_st.cmd_num=1;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
		set_reg_st.value[1] = (0 |0);	//hor_zoom |ver_zoom
		do_mw32 ( (_SET_REG_STR_ ) set_reg_st);
		printk ("[Zoomin : OFF]\n"); 
#endif		
	}
	else 		/*RES_MODE_CIF*/
	{
		/* Input Video Format : 0x01 */
		id_conf = RxID(GID_ENC_VIDEO, 0x00, 0x01, W_FLAG);
		set_reg_st.cmd_num=4;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;		
		set_reg_st.value[1] = 720;		// hor_size
		if (PAL_NTSC==NTSC) {
			set_reg_st.value[2] = 480;	// ver_size
			set_reg_st.value[3] = 7;		// video_input_rate 60000/10001
			set_reg_st.value[4] = 1;		// field_mode (d1=>progressive '1')
			//printk ("[Input video Format 720, 480, 4, 0]\n"); 
		}
		else {
			set_reg_st.value[2] = 576;	// ver_size
			set_reg_st.value[3] = 6;		// video_input_rate 50
			set_reg_st.value[4] = 1;		// field_mode (d1=>progressive '1')
			//printk ("[Input video Format 720, 576, 3, 0]\n"); 		
		}
		do_mw32 ( (_SET_REG_STR_ ) set_reg_st);
		for (clear_cnt=0;clear_cnt<6;clear_cnt++) {set_reg_st.value[clear_cnt]=0;}

 		/*Input  video scale mode*/
		id_conf = RxID(GID_ENC_VIDEO_CH, 0x00, 0x22, W_FLAG);
		set_reg_st.cmd_num=2;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;		
		set_reg_st.value[1] = 2;		// hor_scale 1/2
		set_reg_st.value[2] = 0;		// ver_scale 1/1 progressive
		//set_reg_st.value[2] = 1;	// ver_scale 1/2 interace
		do_mw32 ( (_SET_REG_STR_ ) set_reg_st);		
		//printk ("[Input  video scale mode 50, 100]\n"); 
		
		/*Encoding region information*/
		id_conf = RxID(GID_ENC_VIDEO_CH, 0x00, 0x23, W_FLAG);
		set_reg_st.cmd_num=4;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;		
		set_reg_st.value[1] = 0;			//hor_offset	0
		set_reg_st.value[2] = 0;			//ver_offset	0
		set_reg_st.value[3] = (360>>4);	//hor_MB	0x16
		if (PAL_NTSC==NTSC) {	/*NTSC CIF*/
			set_reg_st.value[4] = (240>>4);	//ver_MB		0x0F
			printk ("[RESOLUTION : NTSC 360x240]\n"); 
		}
		else {		/*PAL CIF*/
			set_reg_st.value[4] = (288>>4);	//ver_MB		0x12
			printk ("[RESOLUTION : PAL 360x288]\n"); 
		}
		do_mw32 ( (_SET_REG_STR_ ) set_reg_st);
		for (clear_cnt=0;clear_cnt<6;clear_cnt++) {set_reg_st.value[clear_cnt]=0;}
		
		id_conf = RxID(GID_ENC_VIDEO_CH, 0x00, 0x24, W_FLAG);
		set_reg_st.cmd_num=2;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;		
		set_reg_st.value[1] = 2;		//Input frames
		set_reg_st.value[2] = 1;		//recoded frames
		do_mw32 ( (_SET_REG_STR_ ) set_reg_st);
		for (clear_cnt=0;clear_cnt<6;clear_cnt++) {set_reg_st.value[clear_cnt]=0;}

		/*Recoding frame rate control*/
		if (frm>=30) frame_rate=30;	
		else if (frm<=1) frame_rate=1;	
		else frame_rate=frm;
		printk ("[FRAME_RATE : %d/SEC]\n" , frame_rate);

#if 0		
		/* Zoomin */
		id_conf = RxID(GID_DEC_VIDEO, 0, 0x10, W_FLAG);	
		set_reg_st.cmd_num=1;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
		set_reg_st.value[1]  = (1 |2);	//hor_zoom  | ver_zoom
		do_mw32 ( (_SET_REG_STR_ ) set_reg_st);
		printk ("[Zoomin : ON]\n"); 
#endif		
	}
	
	udelay(100000);
#ifdef START_STOP_ENC
	for (id_conf=0;id_conf<20;id_conf++) {udelay(100000);}
	id_conf = RxID(GID_ENCODER, 0x00, 0x02, W_FLAG);	
	set_reg_st.cmd_num=1;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
	set_reg_st.value[1]=START_STOP_ENC;
	do_mw32 ( (_SET_REG_STR_ ) set_reg_st);		
#endif

	return ;	
}


/* decoder system parameters */
void video_decoder_cfg(void) 
{
	_SET_REG_STR_ set_reg_st={0,0,{0,0,0,0,0,0}};
	unsigned short id_conf;

	id_conf = RxID(GID_DEC_AUDIO, 0, 0x01, W_FLAG);	
	set_reg_st.cmd_num=1;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
	set_reg_st.value[1]=9;
	
	id_conf = RxID(GID_DEC_AUDIO, 0, 0x03, W_FLAG);	
	set_reg_st.cmd_num=3;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
	set_reg_st.value[1]=0;set_reg_st.value[2]=1;set_reg_st.value[3]=0;
	
	id_conf = RxID(GID_DEC_AUDIO, 0, 0x04, W_FLAG);	
	set_reg_st.cmd_num=1;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
	set_reg_st.value[1]=0;

	id_conf = RxID(GID_DEC_AUDIO, 0, 0x05, W_FLAG);	
	set_reg_st.cmd_num=1;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
	set_reg_st.value[1]=0;
	
	id_conf = RxID(GID_DEC_AUDIO, 0, 0x06, W_FLAG);	
	set_reg_st.cmd_num=1;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
	set_reg_st.value[1]=64;

	id_conf = RxID(GID_DEC_AUDIO, 0, 0x07, W_FLAG);	
	set_reg_st.cmd_num=1;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
	set_reg_st.value[1]=0;
	printk ("[video_decoder_cfg]\n"); 
}

void read_tx_reg (void) 
{
	_SET_REG_STR_ set_reg_st={0,0,{0,0,0,0,0,0}};
	unsigned short id_conf;

	//id_conf = RxID(GID_ENC_AUDIO, 0, 0x01, R_FLAG);	
	id_conf = RxID(GID_ENC_VIDEO, 0x00, 0x01, R_FLAG);
	set_reg_st.cmd_num=0;set_reg_st.addr=AT2041_RX_FIFO_ADDR;set_reg_st.value[0]=id_conf;
	do_mw32 ( (_SET_REG_STR_ ) set_reg_st);		
	printk ("[kernel][read_tx_reg] 0x%x\n", id_conf); 
	
	return ;
}

static int at2041_ioctl (struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
{
	_SET_REG_STR_ set_reg_str={0,0,{0,0,0,0,0,0}};
	unsigned short ioctl_dat=0;
		
	//printk("[at2041_inf]at2041_ioctl : 0x%x\n", cmd);
	
	switch(cmd) {
		//case READ_Tx_FIFO :
		case AT2041_TX_FIFO_ADDR :
			put_user(*tx_buf[txfifo_rd_cnt], (unsigned short *) arg);
			
			/* txfifo ring buffer control */
			if (!txfifo_ring_cnt && txfifo_rd_cnt <= txfifo_wr_cnt) {
				txfifo_rd_cnt ++;
				if (txfifo_rd_cnt == MAX_BUF_NUM) {
					txfifo_ring_cnt --;
					txfifo_rd_cnt = 0;
				}
			} else if (txfifo_ring_cnt) {
				txfifo_rd_cnt ++;
			}
			break; 
			
		case SET_REG:
			copy_from_user( (_SET_REG_STR_ *)&set_reg_str, (unsigned short *)arg , sizeof(_SET_REG_STR_));
			//do_mw32(set_reg_str.addr, set_reg_str.value[0]);
			do_mw32 ( (_SET_REG_STR_ ) set_reg_str);	
			break;
			
#if 1
		//case WRITE_Rx_FIFO :
		case AT2041_RX_FIFO_ADDR :
			//get_user(ioctl_dat, (unsigned short *)arg);
			//do_mw32(AT2041_RX_FIFO_ADDR, ioctl_dat);			
			printk ("AT2041_RX_FIFO_ADDR\n");
			break;	
			
		//case WRITE_COMMAND_REG :
		case AT2041_COMMAND_REG_ADDR :
			//get_user(ioctl_dat, (unsigned short *)arg);
			//do_mw32(AT2041_COMMAND_REG_ADDR, ioctl_dat);			
			printk ("AT2041_COMMAND_REG_ADDR\n");
			break;	

		//case WRITE_CONTROL_REG :
		case AT2041_CONTROL_REG_ADDR :
			//get_user(ioctl_dat, (unsigned short *)arg);
			//do_mw32(AT2041_CONTROL_REG_ADDR, ioctl_dat);			
			printk ("AT2041_CONTROL_REG_ADDR\n");
			break;	         
#endif			
		//case READ_STATUS_REG :
		case AT2041_STATUS_REG_ADDR :
			ioctl_dat = *((unsigned short *)((unsigned int)fifo_reg + AT2041_STATUS_REG));
			printk ("AT2041_STATUS_REG_ADDR : 0x%x\n", ioctl_dat);
			put_user(ioctl_dat, (unsigned short *) arg);
			break;  
			
		case AT2041_TX_FIFO_ADDR_READ :
			read_tx_reg();
			break;  
			
		case AT2041_INIT :
			//at2041_ioctl_init();
			//pre_enc_config();
			break;			

		case SET_CBR:
			copy_from_user( (_SET_REG_STR_ *)&set_reg_str, (unsigned short *)arg , sizeof(_SET_REG_STR_));
			set_cbr(set_reg_str.value[1]);
			break;
		case SET_QUALITY:
			copy_from_user( (_SET_REG_STR_ *)&set_reg_str, (unsigned short *)arg , sizeof(_SET_REG_STR_));
			set_quality(set_reg_str.value[1]);
			break;
		case SET_ENC_MODE:
			copy_from_user( (_SET_REG_STR_ *)&set_reg_str, (unsigned short *)arg , sizeof(_SET_REG_STR_));
			set_enc_mode(set_reg_str.value[1]);
			break;
		case SET_ENC_OPT:
			copy_from_user( (_SET_REG_STR_ *)&set_reg_str, (unsigned short *)arg , sizeof(_SET_REG_STR_));
			set_enc_opt(set_reg_str.value[1]);
			break;
		case SET_RES:
			copy_from_user( (_SET_REG_STR_ *)&set_reg_str, (unsigned short *)arg , sizeof(_SET_REG_STR_));
			set_res(set_reg_str.value[1], set_reg_str.value[2]);
			break;
			
		default :
			break; 
	}
	return 0;
}

static ssize_t muxfifo_read(struct file *file, char *buffer,size_t length,loff_t * offset) 
{
	_SET_REG_STR_ set_reg_st={0,0,{0,0,0,0,0,0}};
	/* copy mux_buf to user space */
	/* real transfer size is size_buf[mux_rd_cnt] * 256bit.
	 * third parameter of copy_to_user() is the 'byte' number to transfer
	 * so, it's calculated size_buf[mux_rd_cnt] * 32
	 */
	unsigned int size;
	
	down(&muxfifo_read_sem);
	
	size = (*size_buf[mux_rd_cnt] << 5) + (enc_txmsg_size << 1);
	//size =(((*size_buf[mux_wr_cnt] & 0xffff) << 4) + enc_txmsg_size)*2;
	copy_to_user(buffer, mux_buf[mux_rd_cnt], size);	
	
	/* multiplex ring buffer control */
	if (!mux_ring_cnt && mux_rd_cnt <= mux_wr_cnt) {
		mux_rd_cnt ++;
		if (mux_rd_cnt == MAX_BUF_NUM) {
			mux_ring_cnt --;
			mux_rd_cnt = 0;
		}
	} 
	else if (mux_ring_cnt) {
		mux_rd_cnt ++;
		if (mux_rd_cnt == MAX_BUF_NUM) {
			mux_ring_cnt --;			
			mux_rd_cnt = 0;
		}		
	}

	if (mux_full) {
		/* acknowledge for data ready message */
		//*((unsigned short *)((unsigned int)fifo_reg + AT2041_RX_FIFO_ADDR)) = 0x8803;
		//do_mw32(AT2041_RX_FIFO_ADDR, 0x8803);
		set_reg_st.cmd_num=0;set_reg_st.addr=AT2041_RX_FIFO_ADDR;
		set_reg_st.value[0]=0x8803;	
		do_mw32 ( (_SET_REG_STR_ ) set_reg_st);		
		
		mux_full = 0;
	}	
		
	return 0;
}

static ssize_t demuxfifo_write(struct file *file,const char *buffer, size_t length, loff_t * offset)
{
	down(&demuxfifo_write_sem);

	copy_from_user(demux_buf[demux_wr_cnt], buffer, length);
	
	demux_size_buf[demux_wr_cnt] = length;

	/* de-multiplex ring buffer control */
	if (!demux_ring_cnt) {
		demux_wr_cnt ++;
		if (demux_wr_cnt == MAX_BUF_NUM) {
			demux_ring_cnt ++;