at2041_api.c

这个是Linux下的应用程序

{
	rx_id = RxID(GID_DEC, 0x00, PID_DEC_STOP, W_FLAG);
	write_parm(rx_id, mode);
	printf ("video_decoder_stop : 0x%04x\n", mode);
}

void dec_resume(void)
{
	rx_id = RxID(GID_DEC, 0x00, PID_DEC_RESUME, W_FLAG);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
}

void dec_pause(void)
{
	rx_id = RxID(GID_DEC, 0x00, PID_DEC_PAUSE, W_FLAG);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
}

void input_stream_format(uns16 format)
{
	/* format : '1' ES or Data, '2' PES or PS, '3' TS, default is '1'
	 */
	rx_id = RxID(GID_DEC, 0x00, PID_DEC_STR_FMT, W_FLAG);
	write_parm(rx_id, format);
}

void sync_lock_count_number(uns16 number)
{
	/* number : '0' ~ '7', default is '3'
	 *          This is valid only if the input stream format is TS
	 */
	rx_id = RxID(GID_DEC, 0x00, PID_DEC_SLOCK_NUM, W_FLAG);
	write_parm(rx_id, number);
}

void decode_mode(uns16 mode)
{
        /* mode : '0' real time mode(use time stamp)
         *        '1' non-real time mode(not use time stamp)
         *         default is real time mode
         */
        rx_id = RxID(GID_DEC, 0x00, PID_DEC_MODE, W_FLAG);
        write_parm(rx_id, mode);
}

// pentamicro 2005.07.28
void decoder_stc_speed_control(uns16 speed)
{
        /* speed :  -15 - 15        
         */
        rx_id = RxID(GID_DEC, 0x00, PID_DEC_STC_SPEED_CONTROL, W_FLAG);
        write_parm(rx_id, speed);
}

// pentamicro 2005.07.28
void decoder_av_input_buffer_depth_control(uns16 video_depth, uns16 audio_depth)
{
        /* video_depth :  0 - 15
        	audio_depth : 0 - 15
         */
        rx_id = RxID(GID_DEC, 0x00, PID_DEC_AV_BUFFER_DEPTH_CONTROL, W_FLAG);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &video_depth);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &audio_depth);
}


/* decoder video parameters */
void output_video_format(uns16 format)
{
        /* format : '0' NTSC, '1' PAL, default is '0'   */
        rx_id = RxID(GID_DV, 0x00, PID_DV_FMT, W_FLAG);
        write_parm(rx_id, format);
}

void output_video_clock_inversion(uns16 mode)
{
	/* mode : '0' use input clock
	 *        '1' use inverted input clock
	 *        default is '0'
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_CLK_INV, W_FLAG);
        write_parm(rx_id, mode);
}

void video_interface_mode(uns16 mode)
{
	/* mode : '0' master, '1' slave, default is '0' */
        rx_id = RxID(GID_DV, 0x00, PID_DV_SLAVE, W_FLAG);
        write_parm(rx_id, mode);
}

void dec_vertical_offset_mode(uns16 ef_voffset, uns16 of_voffset)
{
	/* ef_voffset : vertical offset for even field, default is 284
	 * of_voffset : vertical offset for odd field, default is 21
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_VOFF, W_FLAG);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &ef_voffset);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &of_voffset);
}

void dec_field_sync_mode(uns16 mode)
{
	/* mode : '0' generate field sync using the 'first field decision parameter'
	 *        '1' use field sync input
	 *        default is '0'
	 *        This is vlaid only if slave mode is 1
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_FSYNC_M, W_FLAG);
        write_parm(rx_id, mode);
}

void first_field_decision_parameter(uns16 value)
{
	/* This is valid only if the field sync mode is 0.
	 * if the number of clock cycles between the start of vertical sync 
	 * and the start of horizontal sync falling is less than or equal this value,
	 * the next field is the first field.
	 *
	 * default is 128
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_FSYNC_P, W_FLAG);
        write_parm(rx_id, value);
}

#if 0		/* 2005-04-07 netbsd */
void horizontal_sync_control(uns16 hsync_start_position, uns16 hsync_end_position)
{
	/* hsync_start_position : horizontal sync start position
	 *                        default is 28
	 * hsync_end_position : horizontal sync end position
	 *                      default is 159
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_HSYNC_CTRL, W_FLAG);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &hsync_start_position);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &hsync_end_position);
}
#else
void horizontal_sync_control(uns16 hsync_start_position, uns16 hsync_end_position, uns16 hsync_to_end_cycle)
{
	/* hsync_start_position : horizontal sync start position
	*                        default is 28
	* hsync_end_position : horizontal sync end position
	*                      default is 159
	*/
	rx_id = RxID(GID_DV, 0x00, PID_DV_HSYNC_CTRL, W_FLAG);
	ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
	ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &hsync_start_position);
	ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &hsync_end_position);
	ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &hsync_to_end_cycle);
}
#endif

void vertical_sync_control(uns16 start_line_number_ff, uns16 end_line_number_ff, 
	uns16 transition_position_ff, uns16 start_line_number_sf, 
	uns16 end_line_number_sf, uns16 transition_position_sf)
{
	/* start_line_number_ff   : vertical sync start line number of the first field
	 *                          default is 3
	 * end_line_number_ff     : vertical sync end line number of the first field
	 *                          default is 7
	 * transition_position_ff : vertical sync transition position of the first field,
	 *                          this value means the offset cycles from the end of
	 *                          horizontal valid to the vercical sync transition position
	 *                          default is 90
	 * start_line_number_sf   : vertical sync start line number of the second field
	 *                          default is 265
	 * end_line_number_sf     : vertical sync end line number of the second field
	 *                          default is 268
	 * transition_position_sf : vertical sync transition position of the second field
	 *                          default is 855
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_VSYNC_CTRL, W_FLAG);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &start_line_number_ff);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &end_line_number_ff);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &transition_position_ff);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &start_line_number_sf);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &end_line_number_sf);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &transition_position_sf);
}

void field_sync_control(uns16 start_line_number_ff, uns16 start_line_number_sf, 
			uns16 transition_position)
{
	/* start_line_number_ff : the first field start line number
	 *                        default is 3
	 * start_line_number_sf : the second field start line number
	 *                        default is 265
	 * transition_position  : field sync transition position
	 *                        this value means the offset cycles from the end of horizontal
	 *                        valid to the field sync transition position
	 *                        default is 31
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_FSYNC_CTRL, W_FLAG);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &start_line_number_ff);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &start_line_number_sf);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &transition_position);
}

void video_output_sync_polarity(uns16 hvalid, uns16 hsync, uns16 vvalid, uns16 vsync, uns16 fsync)
{
	/* hvalid : horizontal valid polarity
	 *          '0' active low, '1' active high, default is '1'
	 * hsync  : horizontal sync polarity
	 *          '0' active high, '1' active low, default is '0'
	 * vvalid : vertical valid polarity
	 *          '0' active low, '1' active high, default is '1'         
	 * vsync  : vertical sync polarity
	 *          '0' active high, '1' active low, default is '0'
	 * fsync  : field sync value of the first field
	 *          default is '0'
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_SYNC_POL, W_FLAG);
	rx_data = (fsync << 4) | (vsync << 3) | (vvalid << 2) | (hsync << 1) | hvalid;
        write_parm(rx_id, rx_data);

}

void output_video_data_saturation_value(uns16 min_luma, uns16 max_luma, 
					uns16 min_chroma, uns16 max_chroma)
{
	/* min_luma   : minimum value of luminance data
	 *              default is 16
	 * max_luma   : maximum value of luminance data
	 *              defalue is 235
	 * min_chroma : minimum value of chrominance data
	 *              default is 16
	 * max_chroma : maximum value of chrominance data
	 *              defalue is 239
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_DATA_SAT, W_FLAG);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &min_luma);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &max_luma);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &min_chroma);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &max_chroma);
}

void zoom_in(uns16 horizontal_direction, uns16 vertical_direction)
{
	/* horizontal_direction : '0' original, '1' horizontal zoom_in(x2), defaule is '0'
	 * vertical_direction : '0' original, '1' vertical zoom_in(x2), defaule is '0'
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_ZOOM_IN, W_FLAG);
	rx_data = (vertical_direction << 1) | horizontal_direction;
        write_parm(rx_id, rx_data);
}

void partial_display_zoom_offset(uns16 hoffset, uns16 voffset)
{
	/* hoffset : horizontal offset, 16-pel unit, default is 0
	 * voffset : vertical offset, 2-line unit, default is 0
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_ZOOM_OFF, W_FLAG);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &hoffset);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &voffset);
}

void deinterlace_mode(uns16 mode)
{
	/* mode : '0' disable, '1' enable, default is '0' */
        rx_id = RxID(GID_DV, 0x00, PID_DV_DINT_EN, W_FLAG);
        write_parm(rx_id, mode);
}

void field_repeat_output_mode(uns16 mode)
{
	/* mode : '0' disable, '1' enable, default is '0' */
        rx_id = RxID(GID_DV, 0x00, PID_DV_FLD_RPT, W_FLAG);
        write_parm(rx_id, mode);
}

void vbi_encod_mode(uns16 mode)
{
	/* mode : '0' off, '1' AT204xE VBI mode, default is '0' */
        rx_id = RxID(GID_DV, 0x00, PID_DV_VBI_MODE, W_FLAG);
        write_parm(rx_id, mode);
}

void colorbar_mode(uns16 mode)
{
	/* mode : '0' off, '1' on, default is '0' */
        rx_id = RxID(GID_DV, 0x00, PID_DV_COLOR_BAR, W_FLAG);
        write_parm(rx_id, mode);
}

void borderline_mode(uns16 mode)
{
	/* mode : '0' off, '1' on, default is '0' */
        rx_id = RxID(GID_DV, 0x00, PID_DV_BL_EN, W_FLAG);
        write_parm(rx_id, mode);
}

void borderline_color(uns16 Y, uns16 Cb, uns16 Cr)
{
	/* Y : default is 128
	 * Cb : default is 128
	 * Cr : default is 128
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_BL_COLOR, W_FLAG);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &Y);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &Cb);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &Cr);
}

void background_color_display_mode(uns16 mode)
{
	/* mode : '0' off, '1' on, default is '0' */
        rx_id = RxID(GID_DV, 0x00, PID_DV_BC_EN, W_FLAG);
        write_parm(rx_id, mode);
}

void background_color(uns16 Y, uns16 Cb, uns16 Cr)
{
	/* Y : this value * 4, default is 32
	 * Cb : this value * 8, default is 16
	 * Cr : this value * 8, default is 16
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_BC_COLOR, W_FLAG);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &Y);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &Cb);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &Cr);
}

void foreground_video_window(uns16 h_start_position, uns16 v_start_position, 
	uns16 h_end_position, uns16 v_end_position)
{
	/* h_start_position : horizontal start position (pixel unit), default is 20
	 * v_start_position : vertical start position (2-line unit), default is 10
	 * h_end_position   : horizontal end position ( pixel unit), defualt is 700
	 * v_end_position   : vertical end position (2-line unit), default is 230
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_FG_WINDOW, W_FLAG);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &h_start_position);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &v_start_position);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &h_end_position);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &v_end_position);
}

void background_image_download_start(void)
{
       rx_id = RxID(GID_DV, 0x00, PID_DV_BI_DN_STT, W_FLAG);
       //ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
	ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
}

void background_image_download_finish(void)
{
        rx_id = RxID(GID_DV, 0x00, PID_DV_BI_DN_FIN, W_FLAG);
        //ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
	 ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
}

void background_image_cpature(void)
{
        rx_id = RxID(GID_DV, 0x00, PID_DV_BI_CAP, W_FLAG);
        //ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
        ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
}

void background_image_display_mode(uns16 mode)
{
	/* mode : 
	 *        '0' background image display mode
	 *        '1' input video monitor mode
	 *        default is '0'
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_BI_MODE, W_FLAG);
        write_parm(rx_id, mode);
}

void monitor_channel_id(uns16 ch_id)
{
	/* this is valid only if the background image display mode is '2' */
        rx_id = RxID(GID_DV, 0x00, PID_DV_BI_MCID, W_FLAG);
        write_parm(rx_id, ch_id);
}

// pentamicro 2005.07.28
void decoder_low_delay_display(uns16 value)
{
        /* 1: low delay, 0 : normal        
         */
        rx_id = RxID(GID_DV, 0x00, PID_DVC_LOW_DEALY_DISPLAY, W_FLAG);
        write_parm(rx_id, value);
}

void step_mode(uns16 mode)
{
	/* mode : '0' FWD, '1' BWD */
        rx_id = RxID(GID_DV, 0x00, PID_DV_STEP, W_FLAG);
        write_parm(rx_id, mode);
}

/* Decoder video channel parameters */
void decode_standard(uns16 ch_id, uns16 standard)
{
	/* ch_id    : channel ID
	 * standard : '0' JPEG, '1' MPEG1, '2' MPEG2, '3' H.263, '4' MPEG4
	 *            default is '4'
	 */
        rx_id = RxID(GID_DVC, ch_id, PID_DVC_STD, W_FLAG);
        write_parm(rx_id, standard);
}

void set_vid_stream_id(uns16 ch_id, uns16 ID)
{
	/* ch_id : channel ID
	 * ID    : default is 0
	 *        - Stream ID : If the input stream format is PES or PS then 0 ~ 15
	 *        - PID       : If the input stream format is not TS then 0x0010 ~ 0x1FFE
	 */
        rx_id = RxID(GID_DVC, ch_id, PID_DVC_STR_ID, W_FLAG);
        write_parm(rx_id, ID);
}

void freeze(uns16 ch_id, uns16 mode)
{
	/* ch_id : channel ID
	 * mode  : '0' off, '1' on, default is '0'
	 */
        rx_id = RxID(GID_DVC, ch_id, PID_DVC_FREEZE, W_FLAG);
        write_parm(rx_id, mode);
}

void display(uns16 ch_id, uns16 mode)
{
	/* ch_id : channel ID
	 * mode  : '0' off, '1' on, default is '0'
	 */
        rx_id = RxID(GID_DVC, ch_id, PID_DVC_DISP, W_FLAG);
        write_parm(rx_id, mode);
}

void scale_down_mode(uns16 ch_id, uns16 hscale, uns16 vscale)
{
	/* ch_id : channel ID
	 * hscale : horizontal scale-down mode, default is '0'
	 *          '0' 1, '1' 1/2, '2' 1/3, '3' 1/4, '4' 2/3
	 * vscale : vertical scale-down mode, default is '0'
	 *          '0' 1, '1' 1/2, '2' 1/3, '3' 1/4, '4' 2/3
	 */
       rx_id = RxID(GID_DVC, ch_id, PID_DVC_SCL_DN, W_FLAG);
	ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &rx_id);
       ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &hscale);
       ioctl(at2042_fd, AT2041_RX_FIFO_ADDR, &vscale);
}

void display_offset(uns16 ch_id, uns16 hoffset, uns16 voffset)