📄 globaldef.h
字号:
/***********************************************************************
// Name : GlobalDef.h
// Organization : Hunan University
// Author : Huangzhi
// Date : 2007.09.1
// Description : Global definition mainly for hardware and application
// Version : V1.0
// History :
************************************************************************/
#ifndef GLOBALDEF_H
#define GLOBALDEF_H
#define DBG_MSG(a) PrintString(0, a)
#define uchar unsigned char
#define uint unsigned int
#define AD_QUE_LEN 4
#define PUMP_NUM 4
#define DISP_UP_LIMITS 120
#define DISP_LO_LIMITS -100
#define ENGINE_IDLE_SPD 70
#define ENGINE_MAX_SPD 250
#define ENGINE_WORK_SPD 100
#define ENGINE_SPD_P1 185
#define ENGINE_SPD_P2 250
#define ST_RESET 0
#define ST_4WD 1
#define ST_2WD 2
#define ST_BRAKE 4
#define ST_REVERSE 8
#define FORWARD 1
#define BACK -1
#define ACCELERATION 4
#define DECELERATION 4
#define MAX_SERVO_SPD 127
#define MIN_SERVO_SPD (DECELERATION +2)
#define ACC_DIST 6 // accelerate when dist > 4, decelerate when dist <=4
typedef struct PUMP_CTL{
int Cur;
int Dest;
uchar Count;
uchar Spd;
};
#define PRIVATE static
// interruption vector
#define VEC_RST 0 // RESET
#define VEC_CMF 1 // Clock Monitor fail reset
#define VEC_COP 2 // COP failure Reset
#define VEC_UIINS 3 // Unimplemented instruction trap
#define VEC_SWI 4 // SWI
#define VEC_XIRQ 5 // XIRQ
#define VEC_IRQ 6 // IRQ
#define VEC_RTI 7 // Real Time Interrupt
#define VEC_ECT0 8 // Enhanced Capture Timer channel 0
#define VEC_ECT1 9 // Enhanced Capture Timer channel 1
#define VEC_ECT2 10 // Enhanced Capture Timer channel 2
#define VEC_ECT3 11 // Enhanced Capture Timer channel 3
#define VEC_ECT4 12 // Enahnced Capture Timer channel 4
#define VEC_ECT5 13 // Enhanced Capture Timer channel 5
#define VEC_ECT6 14 // Enhanced Capture Timer channel 6
#define VEC_ECT7 15 // Enhanced Capture Timer channel 7
#define VEC_ECTO 16 // Enhanced Capture Timer overflow
#define VEC_PAAO 17 // Pulse accumulator A overflow
#define VEC_PAIE 18 // Pulse accumulator input edge
#define VEC_SPI0 19 // SPI0
#define VEC_SCI0 20 // SCI0
#define VEC_SCI1 21 // SCI1
#define VEC_ATD0 22 // ATD0
#define VEC_ATD1 23 // ATD1
#define VEC_PIEJ 24 // PORT J
#define VEC_PIEH 25 // PORT H
#define VEC_MDCU 26 // Modulus Down Counter underflow
#define VEC_PABO 27 // Pulse Accumulator B Overflow
#define VEC_CRGLOCK 28 // CRG PLL Lock
#define VEC_CRGSL 29 // CRG Self Clock Mode
#define VEC_BDLC 30 // BDLC
#define VEC_IIC 31 // IIC Bus
#define VEC_SPI1 32 // SPI1
// SPI2
#define VEC_EEPROM 34 // EEPROM
#define VEC_FLASH 35 // FLASH
#define VEC_CAN0WAKE 36 // CAN0 wake-up
#define VEC_CAN0ER 37 // CAN0 errors
#define VEC_CAN0R 38 // CAN0 receive
#define VEC_CAN0T 39 // CAN0 transmit
#define VEC_CAN1UP 40 // CAN1 wake-up
#define VEC_CAN1ER 41 // CAN1 errors
#define VEC_CAN1R 42 // CAN1 receive
#define VEC_CAN1T 43 // CAN1 transmit
#define VEC_BFRF 44
#define VEC_BFR 45
#define VEC_BFSY 46
#define VEC_BF 47
#define VEC_CAN4WAKE 52 // CAN4 wake-up
#define VEC_CAN4ER 53 // CAN4 errors
#define VEC_CAN4R 54 // CAN4 receive
#define VEC_CAN4T 55 // CAN4 transmit
#define VEC_PIEP 56 // PORT P Interrupt
#define VEC_PWMOFF 57 // PWM Emergency Shutdown
// const MACRO
#define TRUE 1
#define FALSE 0
#define OK 0x01
// clock configuration
// set the following values according to system requirements:
#define S12_OSCCLK 16000000 // input frequency from Xtal/Osc
#define S12_REFCLK 8000000 // PLL internal reference clock
#define S12_PLLCLK 48000000 // desired output frequency of PLL
// PLL clock generation formula, according to CRG Block User Guide:
// PLLCLK = OSCCLK * 2(SYNR+1) / (REFDV+1)
//
#define S12_REFDV ((S12_OSCCLK/S12_REFCLK)-1)
#define S12_SYNR ((S12_PLLCLK/(2*S12_REFCLK))-1)
#define S12_ECLK (S12_PLLCLK/2) // final bus clock frequency (ECLK)
//#define S12_ECLK (S12_OSCCLK/2) // bus clock if PLL not in use / off
//-- CRG Bit Mask Definitions -------------------------------------------------
// Bits in CRGFLG:
#define BM_RTIF 0x80
#define BM_PORF 0x40
//#define reserved 0x20
#define BM_LOCKIF 0x10
#define BM_LOCK 0x08
#define BM_TRACK 0x04
#define BM_SCMIF 0x02
#define BM_SCM 0x01
//#define reserved 0x40
//#define reserved 0x20
#define BM_LOCKIE 0x10
//#define reserved 0x08
//#define reserved 0x04
#define BM_SCMIE 0x02
//#define reserved 0x01
// Bits in CLKSEL:
#define BM_PLLSEL 0x80
#define BM_PSTP 0x40
#define BM_SYSWAI 0x20
#define BM_ROAWAI 0x10
#define BM_PLLWAI 0x08
#define BM_CWAI 0x04
#define BM_RTIWAI 0x02
#define BM_COPWAI 0x01
// Bits in PLLCTL:
#define BM_CME 0x80
#define BM_PLLON 0x40
#define BM_AUTO 0x20
#define BM_ACQ 0x10
// Bits in CRGINT
#define BM_RTIE 0x80
#define BM_LOCKIE 0x10
#define BM_SCMIE 0x02
// Bits in RTICTL
#define BM_RTR 0x33; // osc_clk=16000000, RTI period= 1.024ms, RT prescale= 16*1024
//#define reserved 0x08
#define BM_PRE 0x04
#define BM_PCE 0x02
#define BM_SCME 0x01
// Bits in COPCTL
#define BM_RSBCK 0x40
// ECT definitions
#define MDC_PERIOD 10 // ms
#define MDC_PRESCALE 16
#define MDC_PRSEL 0x03
#define TIMER_MDC_COUNT (S12_ECLK/MDC_PRESCALE / 1000 * MDC_PERIOD - 1)
#define TEN (1<<7)
#define TSFRZ (1<<5)
// SCI configuration
#define BR2400 (S12_ECLK/16/2400)
#define BR4800 (S12_ECLK/16/4800)
#define BR9600 (S12_ECLK/16/9600)
#define BR19200 (S12_ECLK/16/19200)
#define BR38400 (S12_ECLK/16/38400)
#define BR57600 (S12_ECLK/16/57600)
#define BR115200 (S12_ECLK/16/115200)
#define DEBUG_BAUD_RATE BR19200
#define BM_TEN 0x80
#define BM_TSWAI 0x40
#define BM_TSBCK 0x20
#define BM_TFFCA 0x10
#define BM_TDRE 0x80
#define BM_TC 0x40
#define BM_RDRF 0x20
#define BM_IDLE 0x10
#define BM_OR 0x08
#define BM_NF 0x04
#define BM_FE 0x02
#define BM_PF 0x01
#define BM_TIE 0x80
#define BM_TCIE 0x40
#define BM_RIE 0x20
#define BM_ILIE 0x10
#define BM_TE 0x08
#define BM_RE 0x04
#define BM_RWU 0x02
#define BM_SBK 0x01
// ATD configuration
// Bits in ATDCTL2
#define BM_ADPU (1<<7)
#define BM_AFFC (1<<6)
#define BM_AWAI (1<<5)
#define BM_ETRIGLE (1<<4)
#define BM_ETRIGP (1<<3)
#define BM_ETRIGE (1<<2)
#define BM_ASCIE (1<<1)
#define BM_ASCIF (1<<0)
#define BM_A
// Bits in ATDCTL3
#define BM_S8C (1<<6)
#define BM_S4C (1<<5)
#define BM_S2C (1<<4)
#define BM_S1C (1<<3)
#define BM_FIFO (1<<2)
#define BM_CONTINUE (0)
#define BM_FIN_FRZ (2)
#define BM_FREEZE (3)
// Bits in ATDCTL4
#define BM_SRES8 (1<<7)
#define BM_2ST (0<<5)
#define BM_4ST (1<<5)
#define BM_8ST (2<<5)
#define BM_16ST (3<<5)
#define BM_PRS(n) (n) // clock = S12_ECLK/(2*(PRS+1))
// Bits in ATDCTL5
#define BM_DJM (1<<7)
#define BM_DSGN (1<<6)
#define BM_SCAN (1<<5)
#define BM_MULT (1<<4)
#define BM_CC (1<<2)
#define BM_CB (1<<1)
#define BM_CA (1<<0)
#define BM_STAN(n) (n)
#define START_AD0 ATD0CTL5 =(BM_DJM+ BM_MULT + 3) // right justification, unsigned, 3~6 channel
#define START_AD1 ATD1CTL5 =(BM_DJM+ BM_MULT + 4) // right justification, unsigned, 12~15 channel
// Bits in ATDSTAT0
#define BM_SCF (1<<7)
#define BM_ETORF (1<<5)
#define BM_FIFOR (1<<4)
// Bits in ATDDIEN
// IO configuration
// PB0: MC0_Dir PB1: MC0_Pulse
// PB2: MC1_Dir PB3: MC1_Pulse
// PB4: MC2_Dir PB5: MC2_Pulse
// PH2: MC3_Dir PH3: MC3_Pulse
// PH0: WD_CTL PH1: ENABLE_START
// PK0: MC0_Low PK1: MC0_Zero PK2: MC0_Up
// PK3: MC1_Low PK4: MC1_Zero PK5: MC1_Up
// PT5: MC2_Low PT6: MC2_Zero PT7: MC2_Up
// PE0: MC3_Low PE2: MC3_Zero PE3: MC3_Up
// !!! PK0~PK2 PE2-PE3 are active when connected to VCC
// !!! the others are active when connected to GND
// PT0: MC0_Spd PT1: MC1_Spd PT2: MC2_Spd PT3: MC3_Spd
// IRQ(PE1): ENG_Spd
// PT4: SW_Brake PM5: SW_BACK
// PM2: SW_WD PM3: SW_CLUTCH
// AN3: Pressure0 AN4: Pressure1 AN5:Pressure2 AN6: Pressure3
// AN12~AN15: measure pump's displacement
#define SET_MC0_DIR (PORTB |= 0x01)
#define CLR_MC0_DIR (PORTB &= (~0x01))
#define SET_MC0_P (PORTB |= 0x02)
#define CLR_MC0_P (PORTB &= (~0x02))
#define SET_MC1_DIR (PORTB |= 0x04)
#define CLR_MC1_DIR (PORTB &= (~0x04))
#define SET_MC1_P (PORTB |= 0x08)
#define CLR_MC1_P (PORTB &= (~0x08))
#define SET_MC2_DIR (PORTB |= 0x10)
#define CLR_MC2_DIR (PORTB &= (~0x10))
#define SET_MC2_P (PORTB |= 0x20)
#define CLR_MC2_P (PORTB &= (~0x20))
#define SET_MC3_DIR (PTH |= 0x04)
#define CLR_MC3_DIR (PTH &= (~0x04))
#define SET_MC3_P (PTH |= 0x08)
#define CLR_MC3_P (PTH &= (~0x08))
#define SET_2WD (PTH |= 0x01)
#define SET_4WD (PTH &= (~0x01))
#define ENABLE_START (PTH |= 0x02)
#define DISABLE_START (PTH &= (~0x02))
#define RELEASE 0
#define MC0_LOW ((PORTK & (1<<0))==0 )
#define MC0_ZERO ((PORTK & (1<<1))==0 )
#define MC0_UP ((PORTK & (1<<2))==0 )
#define MC1_LOW (PORTK & (1<<3))
#define MC1_ZERO (PORTK & (1<<4))
#define MC1_UP (PORTK & (1<<5))
#define MC2_LOW (PTT & (1<<5))
#define MC2_ZERO (PTT & (1<<6))
#define MC2_UP (PTT & (1<<7))
#define MC3_LOW (PORTE & (1<<0))
#define MC3_ZERO ((PORTE & (1<<2))==0 )
#define MC3_UP ((PORTE & (1<<3))==0 )
#define SW_BRAKE (PTT & (1<<4))
#define SW_BACK ((PTM & (1<<5))==0 )
#define SW_4WD (PTM & (1<<2))
#define SW_CLUTCH ((PTM & (1<<3))==0)
#endif
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -