hcs12db128.h

ucos2 应用

/**********************************************************************************  
// Name         :  hcs12db128.h
// Organization :  UNKNOWN
// Author       :  UNKNOWN
// Date         :  UNKNOWN
// Description  :  Macro definition for m9s12db128 hardware
// Version      :  V1.1
// History      :
// revised date         reason                              version     author
// 2007.09.01           add special register definition     V1.1        huangzhi

**********************************************************************************/





#ifndef __HCS12DB128_H
#define __HCS12DB128_H


/* base address of register block, change this if you relocate the register
 * block. This is for S12DB128
 */ 

#define _REG_BASE       0x00


#define _ADDR(off)      (unsigned char volatile *)    (_REG_BASE + off)
#define _REG(off)       *(unsigned char volatile *)   (_REG_BASE + off)
#define _LREG(off)      *(unsigned short volatile *)  (_REG_BASE + off)

#define PORTA   _REG(0x00)
#define PORTB   _REG(0x01)
#define DDRA    _REG(0x02)
#define DDRB    _REG(0x03)

//#define Reserved      _REG(0x04)
//#define Reserved      _REG(0x05)
//#define Reserved      _REG(0x06)
//#define Reserved      _REG(0x07)

#define PORTE   _REG(0x08)
#define DDRE    _REG(0x09)
#define PEAR    _REG(0x0A)
#define MODE    _REG(0x0B)
#define PUCR    _REG(0x0C)
#define RDRIV   _REG(0x0D)
#define EBICTL  _REG(0x0E)

//#define reserved      _REG(0x0F)

#define INITRM  _REG(0x10)
#define INITRG  _REG(0x11)
#define INITEE  _REG(0x12)
#define MISC    _REG(0x13)
//#define MTST0   _REG(0x14)
#define ITCR    _REG(0x15)
#define ITEST   _REG(0x16)
#define MIST1   _REG(0x17)

//#define Reserved      _REG(0x18)
//#define Reserved      _REG(0x19)

#define PARTIDH  _REG(0x1A)
#define PARTIDL  _REG(0x1B)
#define PARTID   _LREG(0x1A)

#define MEMSIZ0  _REG(0x1C)
#define MEMSIZ1  _REG(0x1D)
#define IRQCR    _REG(0x1E)
#define HPRIO    _REG(0x1F)

//#define Reserved      _REG(0x20)
//#define Reserved      _REG(0x21)
//#define Reserved      _REG(0x22)
//#define Reserved      _REG(0x23)
//#define Reserved      _REG(0x24)
//#define Reserved      _REG(0x25)
//#define Reserved      _REG(0x26)
//#define Reserved      _REG(0x27)

#define BKPCT0   _REG(0x28)
#define BKPCT1   _REG(0x29)
#define BKP0X    _REG(0x2A)
#define BKP0H    _REG(0x2B)
#define BKP0L    _REG(0x2C)
#define BKP0     _LREG(0x2B)

#define BKP1X    _REG(0x2D)
#define BKP1H    _REG(0x2E)
#define BKP1L    _REG(0x2F)
#define BKP1     _LREG(0x2E)

#define PPAGE     _REG(0x30)

//#define Reserved      _REG(0x31)

#define PORTK    _REG(0x32)
#define DDRK     _REG(0x33)

#define SYNR     _REG(0x34)
#define REFDV    _REG(0x35)
#define CTFLG    _REG(0x36)
#define CRGFLG   _REG(0x37)
#define CRGINT   _REG(0x38)
#define CLKSEL   _REG(0x39)
#define PLLCTL   _REG(0x3A)
#define RTICTL   _REG(0x3B)
#define COPCTL   _REG(0x3C)
#define FORBYP   _REG(0x3D)
#define CTCTL    _REG(0x3E)
#define ARMCOP   _REG(0x3F)

#define TIOS     _REG(0x40)
#define TCFORC   _REG(0x41)
#define TOC7M    _REG(0x42)
#define TOC7D    _REG(0x43)

#define TCNT     _LREG(0x44)

#define TSCR1    _REG(0x46)
#define TTOV     _REG(0x47)
#define TCTL1    _REG(0x48)
#define TCTL2    _REG(0x49)
#define TCTL3    _REG(0x4A)
#define TCTL4    _REG(0x4B)
#define TIE      _REG(0x4C)
#define TSCR2    _REG(0x4D)
#define TFLG1    _REG(0x4E)
#define TFLG2    _REG(0x4F)

#define TC0      _LREG(0x50)
#define TC1      _LREG(0x52)
#define TC2      _LREG(0x54)
#define TC3      _LREG(0x56)
#define TC4      _LREG(0x58)
#define TC5      _LREG(0x5A)
#define TC6      _LREG(0x5C)
#define TC7      _LREG(0x5E)

#define PACTL     _REG(0x60)
#define PAFLG     _REG(0x61)
#define PACN3     _REG(0x62)
#define PACN2     _REG(0x63)
#define PACN1     _REG(0x64)
#define PACN0     _REG(0x65)
#define MCCTL     _REG(0x66)
#define MCFLG     _REG(0x67)
#define ICPAR     _REG(0x68)
#define DLYCT     _REG(0x69)
#define ICOVW     _REG(0x6A)
#define ICSYS     _REG(0x6B)

//#define Reserved      _REG(0x6C)

#define TIMTST     _REG(0x6D)

//#define Reserved      _REG(0x6E)
//#define Reserved      _REG(0x6F)

#define PBCTL   _REG(0x70)
#define PBFLG   _REG(0x71)
#define PA3H    _REG(0x72)
#define PA2H    _REG(0x73)
#define PA1H    _REG(0x74)
#define PA0H    _REG(0x75)

#define MCCNT   _LREG(0x76)
#define TC0H    _LREG(0x78)
#define TC1H    _LREG(0x7A)
#define TC2H    _LREG(0x7C)
#define TC3H    _LREG(0x7E)

#define ATD0CTL0  _REG(0x80)
#define ATD0CTL1  _REG(0x81)
#define ATD0CTL2  _REG(0x82)
#define ATD0CTL3  _REG(0x83)
#define ATD0CTL4  _REG(0x84)
#define ATD0CTL5  _REG(0x85)

//#define ATD0STAT    _LREG(0x86)
#define ATD0STAT0   _REG(0x86)
//#define ATD0STAT1   _REG(0x87)
#define AID0TEST0   _REG(0x88)
#define AID0TEST1   _REG(0x89)

//#define Reserved      _REG(0x8A)
#define ATD0STA1    _REG(0x8B)
//#define Reserved      _REG(0x8C)

#define ATD0DIEN   _REG(0x8D)

//#define Reserved      _REG(0x8E)

#define PORTAD0   _REG(0x8F)

#define ATD0DR0H  _REG(0x90)
#define ATD0DR0L  _REG(0x91)
#define ATD0DR0   _LREG(0x90)

#define ATD0DR1H  _REG(0x92)
#define ATD0DR1L  _REG(0x93)
#define ATD0DR1   _LREG(0x92)

#define ATD0DR2H _REG(0x94)
#define ATD0DR2L _REG(0x95)
#define ATD0DR2  _LREG(0x94)

#define ATD0DR3H _REG(0x96)
#define ATD0DR3L _REG(0x97)
#define ATD0DR3  _LREG(0x96)

#define ATD0DR4H _REG(0x98)
#define ATD0DR4L _REG(0x99)
#define ATD0DR4  _LREG(0x98)

#define ATD0DR5H _REG(0x9A)
#define ATD0DR5L _REG(0x9B)
#define ATD0DR5  _LREG(0x9A)

#define ATD0DR6H _REG(0x9C)
#define ATD0DR6L _REG(0x9D)
#define ATD0DR6  _LREG(0x9C)

#define ATD0DR7H _REG(0x9E)
#define ATD0DR7L _REG(0x9F)
#define ATD0DR7  _LREG(0x9E)

#define PWME     _REG(0xA0)
#define PWMPOL   _REG(0xA1)
#define PWMCLK   _REG(0xA2)
#define PWMPRCLC _REG(0xA3)
#define PWMCAE   _REG(0xA4)
#define PWMCTL   _REG(0xA5)
#define PWMTST   _REG(0xA6)
#define PWMPRSC  _REG(0xA7)
#define PWMSCLA  _REG(0xA8)
#define PWMSCLB  _REG(0xA9)
#define PWMSCNTA _REG(0xAA)
#define PWMSCNTB _REG(0xAB)

#define PWMCNT0  _REG(0xAC)
#define PWMCNT1  _REG(0xAD)
#define PWMCNT2  _REG(0xAE)
#define PWMCNT3  _REG(0xAF)
#define PWMCNT4  _REG(0xB0)
#define PWMCNT5  _REG(0xB1)
#define PWMCNT6  _REG(0xB2)
#define PWMCNT7  _REG(0xB3)

#define PWMPER0  _REG(0xB4)
#define PWMPER1  _REG(0xB5)
#define PWMPER2  _REG(0xB6)
#define PWMPER3  _REG(0xB7)
#define PWMPER4  _REG(0xB8)
#define PWMPER5  _REG(0xB9)
#define PWMPER6  _REG(0xBA)
#define PWMPER7  _REG(0xBB)

#define PWMDTY0  _REG(0xBC)
#define PWMDTY1  _REG(0xBD)
#define PWMDTY2  _REG(0xBE)
#define PWMDTY3  _REG(0xBF)
#define PWMDTY4  _REG(0xC0)
#define PWMDTY5  _REG(0xC1)
#define PWMDTY6  _REG(0xC2)
#define PWMDTY7  _REG(0xC3)

#define PWMSDN   _REG(0xC4)

//#define Reserved      _REG(0xC5)
//#define Reserved      _REG(0xC6)
//#define Reserved      _REG(0xC7)

#define SCI0BDH  _REG(0xC8)
#define SCI0BDL  _REG(0xC9)
#define SCI0BD   _LREG(0xC8)

#define SC0CR1   _REG(0xCA)
#define SCI0CR1  _REG(0xCA)
#define SCI0CR2  _REG(0xCB)

#define SCI0SR1  _REG(0xCC)
#define SC0SR1	SCI0SR1		/* compatability */
#define SC0SR2   _REG(0xCD)
#define SCI0SR2  _REG(0xCD)

#define SCI0DRH  _REG(0xCE)
#define SCI0DRL  _REG(0xCF)
#define SC0DRL	SCI0DRL		/* compatability */
#define SCI0DR   _LREG(0xCE)

#define SCI1BDH  _REG(0xD0)
#define SCI1BDL  _REG(0xD1)
#define SCI1BD   _LREG(0xD0)

#define SCI1CR1   _REG(0xD2)
#define SCI1CR2   _REG(0xD3)
#define SCI1SR1   _REG(0xD4)
#define SCI1SR2   _REG(0xD5)

#define SCI1DRH   _REG(0xD6)
#define SCI1DRL   _REG(0xD7)
#define SCI1DR    _LREG(0xD6)

#define SPI0CR1   _REG(0xD8)
#define SPI0CR2   _REG(0xD9)
#define SPI0BR    _REG(0xDA)
#define SPI0SR    _REG(0xDB)

//#define Reserved      _REG(0xDC)

#define SPI0DR    _REG(0xDD)

//#define Reserved      _REG(0xDE)
//#define Reserved      _REG(0xDF)

#define IBAD    _REG(0xE0)
#define IBFD    _REG(0xE1)
#define IBCR    _REG(0xE2)
#define IBSR    _REG(0xE3)
#define IICDR   _REG(0xE4)

//#define Reserved      _REG(0xE5)
//#define Reserved      _REG(0xE6)
//#define Reserved      _REG(0xE7)

#define DLCBCR1  _REG(0xE8)
#define DLCBSVR  _REG(0xE9)
#define DLCBCR2  _REG(0xEA)
#define DLCBDR   _REG(0xEB)
#define DLCBARD  _REG(0xEC)
#define DLCBRSR  _REG(0xED)
#define DLCSCR   _REG(0xEE)
#define DLCBSCR  _REG(0xEE)
#define DLCBSTAT _REG(0xEF)

//alternate possible names for registers
#define BDLCCR1  _REG(0xE8)
#define BDLCSVR  _REG(0xE9)
#define BDLCCR2  _REG(0xEA)
#define BDLCDR   _REG(0xEB)
#define BDLCARD  _REG(0xEC)
#define BDLCRSR  _REG(0xED)
#define BDLCSCR  _REG(0xEE)
#define BDLCSTAT _REG(0xEF)

#define SPI1CR1  _REG(0xF0)
#define SPI1CR2  _REG(0xF1)
#define SPI1BR   _REG(0xF2)
#define SPI1SR  _REG(0xF3)

//#define Reserved      _REG(0xF4)

#define SPI1DR  _REG(0xF5)

//#define Reserved      _REG(0xF6)
//#define Reserved      _REG(0xF7)

//#define SPI2CR1 _REG(0xF8)
//#define SPI2CR2 _REG(0xF9)
//#define SPI2BR  _REG(0xFA)
//#define SPI2SR  _REG(0xFB)

//#define Reserved      _REG(0xFC)

//#define SPI2DR  _REG(0xFD)

//#define Reserved _REG(0xFE)
//#define Reserved _REG(0xFF)


#define FCLKDIV _REG(0x0100)
#define FSEC    _REG(0x0101)
#define C0BTR0  _REG(0x0102)

//#define Reserved for Factory Test _REG(0x0102)

#define FCNFG  _REG(0x0103)
#define FPROT  _REG(0x0104)
#define FSTAT  _REG(0x0105)
#define FCMD   _REG(0x0106)

//#define Reserved for Factory Test _REG(0x0107)
//#define Reserved for Factory Test _REG(0x0108)
//#define Reserved for Factory Test _REG(0x0109)
//#define Reserved for Factory Test _REG(0x010A)
//#define Reserved for Factory Test _REG(0x010B)

//#define Reserved _REG(0x010C)
//#define Reserved _REG(0x010D)
//#define Reserved _REG(0x010E)