📄 msp430x22x4.h
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/********************************************************************
*
* Standard register and bit definitions for the Texas Instruments
* MSP430 microcontroller.
*
* This file supports assembler and C development for
* MSP430x22x4 devices.
*
* Texas Instruments, Version 1.4
*
* Rev. 1.0, Setup
* Rev. 1.1, Updated names for USCI
* Rev. 1.2, Added missing definitions in OA and ADC10
* Rev. 1.3 Removed bit definitions for ADC10AEx as this are in conflict with ADC10AEx Register
* Removed not existing SWCTL register definition
* Rev. 1.4, added definitions for Interrupt Vectors xxIV
*
********************************************************************/
#ifndef __msp430x22x4
#define __msp430x22x4
#ifdef __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
#endif
#if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */
#error msp430x22x4.h file for use with ICC430/A430 only
#endif
#ifdef __IAR_SYSTEMS_ICC__
#include <in430.h>
#pragma language=extended
#define DEFC(name, address) __no_init volatile unsigned char name @ address;
#define DEFW(name, address) __no_init volatile unsigned short name @ address;
#define DEFXC volatile unsigned char
#define DEFXW volatile unsigned short
#endif /* __IAR_SYSTEMS_ICC__ */
#ifdef __IAR_SYSTEMS_ASM__
#define DEFC(name, address) sfrb name = address;
#define DEFW(name, address) sfrw name = address;
#endif /* __IAR_SYSTEMS_ASM__*/
#ifdef __cplusplus
#define READ_ONLY
#else
#define READ_ONLY const
#endif
/************************************************************
* STANDARD BITS
************************************************************/
#define BIT0 (0x0001)
#define BIT1 (0x0002)
#define BIT2 (0x0004)
#define BIT3 (0x0008)
#define BIT4 (0x0010)
#define BIT5 (0x0020)
#define BIT6 (0x0040)
#define BIT7 (0x0080)
#define BIT8 (0x0100)
#define BIT9 (0x0200)
#define BITA (0x0400)
#define BITB (0x0800)
#define BITC (0x1000)
#define BITD (0x2000)
#define BITE (0x4000)
#define BITF (0x8000)
/************************************************************
* STATUS REGISTER BITS
************************************************************/
#define C (0x0001)
#define Z (0x0002)
#define N (0x0004)
#define V (0x0100)
#define GIE (0x0008)
#define CPUOFF (0x0010)
#define OSCOFF (0x0020)
#define SCG0 (0x0040)
#define SCG1 (0x0080)
/* Low Power Modes coded with Bits 4-7 in SR */
#ifndef __IAR_SYSTEMS_ICC /* Begin #defines for assembler */
#define LPM0 (CPUOFF)
#define LPM1 (SCG0+CPUOFF)
#define LPM2 (SCG1+CPUOFF)
#define LPM3 (SCG1+SCG0+CPUOFF)
#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
/* End #defines for assembler */
#else /* Begin #defines for C */
#define LPM0_bits (CPUOFF)
#define LPM1_bits (SCG0+CPUOFF)
#define LPM2_bits (SCG1+CPUOFF)
#define LPM3_bits (SCG1+SCG0+CPUOFF)
#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
#include <In430.h>
#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */
#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */
#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */
#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */
#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */
#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */
#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */
#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */
#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */
#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */
#endif /* End #defines for C */
/************************************************************
* PERIPHERAL FILE MAP
************************************************************/
/************************************************************
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
************************************************************/
#define IE1_ (0x0000) /* Interrupt Enable 1 */
DEFC( IE1 , IE1_)
#define WDTIE (0x01) /* Watchdog Interrupt Enable */
#define OFIE (0x02) /* Osc. Fault Interrupt Enable */
#define NMIIE (0x10) /* NMI Interrupt Enable */
#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */
#define IFG1_ (0x0002) /* Interrupt Flag 1 */
DEFC( IFG1 , IFG1_)
#define WDTIFG (0x01) /* Watchdog Interrupt Flag */
#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */
#define PORIFG (0x04) /* Power On Interrupt Flag */
#define RSTIFG (0x08) /* Reset Interrupt Flag */
#define NMIIFG (0x10) /* NMI Interrupt Flag */
#define IE2_ (0x0001) /* Interrupt Enable 2 */
DEFC( IE2 , IE2_)
#define UC0IE IE2
#define UCA0RXIE (0x01)
#define UCA0TXIE (0x02)
#define UCB0RXIE (0x04)
#define UCB0TXIE (0x08)
#define IFG2_ (0x0003) /* Interrupt Flag 2 */
DEFC( IFG2 , IFG2_)
#define UC0IFG IFG2
#define UCA0RXIFG (0x01)
#define UCA0TXIFG (0x02)
#define UCB0RXIFG (0x04)
#define UCB0TXIFG (0x08)
/************************************************************
* ADC10
************************************************************/
#define __MSP430_HAS_ADC10__ /* Definition to show that Module is available */
#define ADC10DTC0_ (0x0048) /* ADC10 Data Transfer Control 0 */
DEFC( ADC10DTC0 , ADC10DTC0_)
#define ADC10DTC1_ (0x0049) /* ADC10 Data Transfer Control 1 */
DEFC( ADC10DTC1 , ADC10DTC1_)
#define ADC10AE0_ (0x004A) /* ADC10 Analog Enable 0 */
DEFC( ADC10AE0 , ADC10AE0_)
#define ADC10AE1_ (0x004B) /* ADC10 Analog Enable 1 */
DEFC( ADC10AE1 , ADC10AE1_)
#define ADC10CTL0_ (0x01B0) /* ADC10 Control 0 */
DEFW( ADC10CTL0 , ADC10CTL0_)
#define ADC10CTL1_ (0x01B2) /* ADC10 Control 1 */
DEFW( ADC10CTL1 , ADC10CTL1_)
#define ADC10MEM_ (0x01B4) /* ADC10 Memory */
DEFW( ADC10MEM , ADC10MEM_)
#define ADC10SA_ (0x01BC) /* ADC10 Data Transfer Start Address */
DEFW( ADC10SA , ADC10SA_)
/* ADC10CTL0 */
#define ADC10SC (0x001) /* ADC10 Start Conversion */
#define ENC (0x002) /* ADC10 Enable Conversion */
#define ADC10IFG (0x004) /* ADC10 Interrupt Flag */
#define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */
#define ADC10ON (0x010) /* ADC10 On/Enable */
#define REFON (0x020) /* ADC10 Reference on */
#define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */
#define MSC (0x080) /* ADC10 Multiple SampleConversion */
#define REFBURST (0x100) /* ADC10 Reference Burst Mode */
#define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */
#define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */
#define ADC10SHT0 (0x800) /* ADC10 Sample Hold Select 0 */
#define ADC10SHT1 (0x1000) /* ADC10 Sample Hold Select 1 */
#define SREF0 (0x2000) /* ADC10 Reference Select 0 */
#define SREF1 (0x4000) /* ADC10 Reference Select 1 */
#define SREF3 (0x8000) /* ADC10 Reference Select 2 */
#define ADC10SHT_0 (0*0x800u) /* 4 x ADC10CLKs */
#define ADC10SHT_1 (1*0x800u) /* 8 x ADC10CLKs */
#define ADC10SHT_2 (2*0x800u) /* 16 x ADC10CLKs */
#define ADC10SHT_3 (3*0x800u) /* 64 x ADC10CLKs */
#define SREF_0 (0*0x2000u) /* VR+ = AVCC and VR- = AVSS */
#define SREF_1 (1*0x2000u) /* VR+ = VREF+ and VR- = AVSS */
#define SREF_2 (2*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */
#define SREF_3 (3*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */
#define SREF_4 (4*0x2000u) /* VR+ = AVCC and VR- = VREF-/VEREF- */
#define SREF_5 (5*0x2000u) /* VR+ = VREF+ and VR- = VREF-/VEREF- */
#define SREF_6 (6*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
#define SREF_7 (7*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
/* ADC10CTL1 */
#define ADC10BUSY (0x0001) /* ADC10CTL1 */
#define CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */
#define CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */
#define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select 0 */
#define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select 1 */
#define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select 0 */
#define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select 1 */
#define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select 2 */
#define ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */
#define ADC10DF (0x0200) /* ADC10 Data Format 0:binary 1:2's complement */
#define SHS0 (0x0400) /* ADC10 Sample/Hold Source 0 */
#define SHS1 (0x0800) /* ADC10 Sample/Hold Source 1 */
#define INCH0 (0x1000) /* ADC10 Input Channel Select 0 */
#define INCH1 (0x2000) /* ADC10 Input Channel Select 1 */
#define INCH2 (0x4000) /* ADC10 Input Channel Select 2 */
#define INCH3 (0x8000) /* ADC10 Input Channel Select 3 */
#define CONSEQ_0 (0*2u) /* Single channel single conversion */
#define CONSEQ_1 (1*2u) /* Sequence of channels */
#define CONSEQ_2 (2*2u) /* Repeat single channel */
#define CONSEQ_3 (3*2u) /* Repeat sequence of channels */
#define ADC10SSEL_0 (0*8u) /* ADC10OSC */
#define ADC10SSEL_1 (1*8u) /* ACLK */
#define ADC10SSEL_2 (2*8u) /* MCLK */
#define ADC10SSEL_3 (3*8u) /* SMCLK */
#define ADC10DIV_0 (0*0x20u)
#define ADC10DIV_1 (1*0x20u)
#define ADC10DIV_2 (2*0x20u)
#define ADC10DIV_3 (3*0x20u)
#define ADC10DIV_4 (4*0x20u)
#define ADC10DIV_5 (5*0x20u)
#define ADC10DIV_6 (6*0x20u)
#define ADC10DIV_7 (7*0x20u)
#define SHS_0 (0*0x400u) /* ADC10SC */
#define SHS_1 (1*0x400u) /* TA3 OUT1 */
#define SHS_2 (2*0x400u) /* TA3 OUT0 */
#define SHS_3 (3*0x400u) /* TA3 OUT2 */
#define INCH_0 (0*0x1000u)
#define INCH_1 (1*0x1000u)
#define INCH_2 (2*0x1000u)
#define INCH_3 (3*0x1000u)
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