12ce51x.mdf

Proteus+7.8+元件库

LISA MODEL DESCRIPTION FORMAT 6.1
=================================
Design:   K:\PRODEV\VSM\PIC12\eeprom\12ce51x.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  09/04/02
Modified: 05/07/06

*PROPERTIES,11   
TRACE_CORE=1
TRACE_EEPROM=1
TRACE_INTERRUPT=1
TRACE_LOAD=1
TRACE_MEMORY=1
TRACE_RESET=1
TRACE_SETUP=1
TRACE_SLEEP=1
TRACE_TIMER0=1
TRACE_TIMER1=1
TRACE_WDT=1

*MODELDEFS,0    

*PARTLIST,2    
CPU,PIC12C51X,PIC12C51X,CFGWORD=<CFGWORD>,CLOCK=<CLOCK>,DBG_GENERATE_CLKOUT=<DBG_GENERATE_CLKOUT>,DBG_RANDOM_DMEM=<DBG_RANDOM_DMEM>,DBG_RANDOM_PMEM=<DBG_RANDOM_PMEM>,DBG_STARTUP_DELAY=<DBG_STARTUP_DELAY>,DBG_WAKEUP_DELAY=<DBG_WAKEUP_DELAY>,MODDLL=<MODDLL>,PORTTDHL=<PORTTDHL>,PORTTDLH=<PORTTDLH>,PRIMITIVE=DIGITAL,PRIMTYPE=<PRIMTYPE>,PROGRAM=<PROGRAM>,TRACE_CORE=<TRACE_CORE>,TRACE_INTERRUPT=<TRACE_INTERRUPT>,TRACE_LOAD=<TRACE_LOAD>,TRACE_MEMORY=<TRACE_MEMORY>,TRACE_RESET=<TRACE_RESET>,TRACE_SETUP=<TRACE_SETUP>,TRACE_SLEEP=<TRACE_SLEEP>,TRACE_TIMER0=<TRACE_TIMER0>,TRACE_TIMER1=<TRACE_TIMER1>,TRACE_WDT=<TRACE_WDT>,WDT_PERIOD=<WDT_PERIOD>
EEPROM,EEPROM,EEPROM,ADDRWIDTH=4,ALWAYS_ACK_DATA=1,BLKADDRMASK=0x00,BLKADDRSHIFT=0,BYTETIMING=0,CMDWIDTH=8,DATAWIDTH=8,DVCADDRMASK=0x00,DVCADDRSHIFT=0,INCRADDR=0,MEMSIZE=16,MODDATA="16,255",MODDLL=I2CMEM.DLL,PRIMITIVE=DIGITAL,TD_BUSFREE=1.3u,TD_CLK_ACK=100n,TD_CLK_ENDDATA=100n,TD_CLK_HIGH=600n,TD_CLK_LOW=1.3u,TD_CLK_SDO=900n,TD_CLK_UNACK=100n,TD_DATA_SETUP=100n,TD_RSTART_SETUP=600n,TD_START_HOLD=600n,TD_STOP_SETUP=600n,TD_WP_HOLD=0,TD_WP_SETUP=0,TD_WRITE=1m,TRACE=<TRACE_EEPROM>,WPAGESIZE=1,WPHIGH=0x0007,WPLOW=0x0000

*NETLIST,10   
#00000,2
EEPROM,IP,SCK
CPU,OP,SCL

#00001,2
EEPROM,IO,SDA
CPU,IO,SDA

GP5/OSC1,2
GP5/OSC1,GT
CPU,IO,GP5/OSC1

GP4/OSC2,2
GP4/OSC2,GT
CPU,IO,GP4/OSC2

GP3/$MCLR$,2
GP3/$MCLR$,GT
CPU,IO,GP3/$MCLR$

GP0,2
GP0,GT
CPU,IO,GP0

GP1,2
GP1,GT
CPU,IO,GP1

GP2/T0CKI,2
GP2/T0CKI,GT
CPU,IO,GP2/T0CKI

VDD,2
VDD,GT
CPU,PP,VDD

VSS,2
VSS,GT
CPU,PP,VSS

*GATES,0