74xx869.mdf

Proteus+7.8+元件库

LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   C:\Program Files\Labcenter Electronics\VSM.LIBS\VSM.LIBS SAMPLES\74 SERIES  MODELS DESIGNS\74XX869\74XX869.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  29/04/02
Modified: 06/06/04

*PROPERTIES,4    
FLOAT=FALSE
INIT=0
TGQ=?
TGQB=?

*MAPPINGS,3,VALUE
74AS869 : TDLHXR=35n,TDHLXR=18n, TDLHCQ=12n,  TDHLCQ=16n
74LS869 : TDLHXR=30n,TDHLXR=13n, TDLHCQ=7n,  TDHLCQ=11n
74869 : TDLHXR=55n,TDHLXR=38n, TDLHCQ=32n,  TDHLCQ=36n

*MODELDEFS,0    

*PARTLIST,7    
U1,COUNTER_8,COUNTER_8,INIT=<INIT>,PRIMITIVE=DIGITAL,TGQ=<TGQB>,USEDIR=0
U2,NAND_2,NAND_2,INVERT=D1,PRIMITIVE=DIGITAL,TGQ=<TGQ>
U3,AND_2,AND_2,PRIMITIVE=DIGITAL,TGQ=<TGQ>
U4,DECODER_2_4,DECODER_2_4,ALL=HIGH,PRIMITIVE=DIGITAL,TGQ=<TGQB>,TYPE=BINARY
U5,AND_2,AND_2,PRIMITIVE=DIGITAL,TGQ=<TGQ>
U6,AND_2,AND_2,PRIMITIVE=DIGITAL,TGQ=<TGQ>
U7,AND_3,AND_3,INVERT="D1,D2",PRIMITIVE=DIGITAL,TGQ=<TGQ>

*NETLIST,36   
#00000,2
U1,IP,UCLK
U6,OP,Q

#00001,2
U1,IP,DCLK
U5,OP,Q

#00002,2
U1,IP,CE
U7,OP,Q

#00003,2
U1,IP,LOAD
U4,OP,Q2

#00004,2
U1,IP,RESET
U4,OP,Q0

#00005,1
U1,OP,MIN

#00006,1
U1,OP,MAX

#00007,1
U1,IP,CNTUP

#00008,2
U1,OP,RCO
U2,IP,D0

#00009,2
U2,IP,D1
U3,OP,Q

#00010,2
U4,OP,Q1
U5,IP,D1

#00011,2
U4,OP,Q3
U6,IP,D0

D0,2
D0,IT
U1,IP,D0

D1,2
D1,IT
U1,IP,D1

D2,2
D2,IT
U1,IP,D2

D3,2
D3,IT
U1,IP,D3

Q0,2
Q0,OT
U1,OP,Q0

Q1,2
Q1,OT
U1,OP,Q1

Q2,2
Q2,OT
U1,OP,Q2

Q3,2
Q3,OT
U1,OP,Q3

D4,2
D4,IT
U1,IP,D4

D5,2
D5,IT
U1,IP,D5

D6,2
D6,IT
U1,IP,D6

D7,2
D7,IT
U1,IP,D7

Q4,2
Q4,OT
U1,OP,Q4

Q5,2
Q5,OT
U1,OP,Q5

Q6,2
Q6,OT
U1,OP,Q6

Q7,2
Q7,OT
U1,OP,Q7

$RCO$,2
$RCO$,OT
U2,OP,Q

$ENT$,3
$ENT$,IT
U3,IP,D1
U7,IP,D2

$ENP$,2
$ENP$,IT
U7,IP,D1

S1,2
S1,IT
U4,IP,D1

S0,4
S0,IT
U4,IP,D0
U3,IP,D0
U7,IP,D0

VCC,3
VCC,PR
U4,IP,EN
U1,IP,OE

GND,2
GND,PR
U4,IP,ALL

CLK,3
CLK,IT
U6,IP,D1
U5,IP,D0

*GATES,0