cpu.fnsim.qmsg

来自「微程序模拟CPU实现加减与或异或转移储存等功能。」· QMSG 代码 · 共 45 行 · 第 1/2 页

{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux4 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux4\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux5 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux5\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_kpc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_kpc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_kpc " "Info: Found entity 1: mux_kpc" {  } { { "db/mux_kpc.tdf" "" { Text "D:/altera/72/quartus/cpu/db/mux_kpc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux6 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux6\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux7 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux7\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux8 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux8\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux9 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux9\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux10 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux10\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux11 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux11\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux12 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux12\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux13 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux13\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux14 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux14\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux15 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux15\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux16 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux16\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux17 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux17\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux18 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux18\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 91 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux19 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux19\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 162 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux27 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux27\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 189 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux28 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux28\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 189 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux31 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux31\"" {  } { { "cpu.vhd" "" { Text "D:/altera/72/quartus/cpu/cpu.vhd" 189 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 8 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "195 " "Info: Allocated 195 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 28 13:23:43 2008 " "Info: Processing ended: Fri Nov 28 13:23:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}