mux_kpc.tdf

来自「微程序模拟CPU实现加减与或异或转移储存等功能。」· TDF 代码 · 共 100 行

--lpm_mux CASCADE_CHAIN="IGNORE" DEVICE_FAMILY="Stratix II" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=32 LPM_WIDTH=1 LPM_WIDTHS=5 data result sel
--VERSION_BEGIN 7.2 cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 11 
SUBDESIGN mux_kpc
( 
	data[31..0]	:	input;
	result[0..0]	:	output;
	sel[4..0]	:	input;
) 
VARIABLE
	l1_w0_n0_mux_dataout	:	WIRE;
	l1_w0_n10_mux_dataout	:	WIRE;
	l1_w0_n11_mux_dataout	:	WIRE;
	l1_w0_n12_mux_dataout	:	WIRE;
	l1_w0_n13_mux_dataout	:	WIRE;
	l1_w0_n14_mux_dataout	:	WIRE;
	l1_w0_n15_mux_dataout	:	WIRE;
	l1_w0_n1_mux_dataout	:	WIRE;
	l1_w0_n2_mux_dataout	:	WIRE;
	l1_w0_n3_mux_dataout	:	WIRE;
	l1_w0_n4_mux_dataout	:	WIRE;
	l1_w0_n5_mux_dataout	:	WIRE;
	l1_w0_n6_mux_dataout	:	WIRE;
	l1_w0_n7_mux_dataout	:	WIRE;
	l1_w0_n8_mux_dataout	:	WIRE;
	l1_w0_n9_mux_dataout	:	WIRE;
	l2_w0_n0_mux_dataout	:	WIRE;
	l2_w0_n1_mux_dataout	:	WIRE;
	l2_w0_n2_mux_dataout	:	WIRE;
	l2_w0_n3_mux_dataout	:	WIRE;
	l2_w0_n4_mux_dataout	:	WIRE;
	l2_w0_n5_mux_dataout	:	WIRE;
	l2_w0_n6_mux_dataout	:	WIRE;
	l2_w0_n7_mux_dataout	:	WIRE;
	l3_w0_n0_mux_dataout	:	WIRE;
	l3_w0_n1_mux_dataout	:	WIRE;
	l3_w0_n2_mux_dataout	:	WIRE;
	l3_w0_n3_mux_dataout	:	WIRE;
	l4_w0_n0_mux_dataout	:	WIRE;
	l4_w0_n1_mux_dataout	:	WIRE;
	l5_w0_n0_mux_dataout	:	WIRE;
	data_wire[61..0]	: WIRE;
	sel_wire[4..0]	: WIRE;

BEGIN 
	l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[1..1] # !(sel_wire[0..0]) & data_wire[0..0];
	l1_w0_n10_mux_dataout = sel_wire[0..0] & data_wire[21..21] # !(sel_wire[0..0]) & data_wire[20..20];
	l1_w0_n11_mux_dataout = sel_wire[0..0] & data_wire[23..23] # !(sel_wire[0..0]) & data_wire[22..22];
	l1_w0_n12_mux_dataout = sel_wire[0..0] & data_wire[25..25] # !(sel_wire[0..0]) & data_wire[24..24];
	l1_w0_n13_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[26..26];
	l1_w0_n14_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[28..28];
	l1_w0_n15_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[30..30];
	l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[3..3] # !(sel_wire[0..0]) & data_wire[2..2];
	l1_w0_n2_mux_dataout = sel_wire[0..0] & data_wire[5..5] # !(sel_wire[0..0]) & data_wire[4..4];
	l1_w0_n3_mux_dataout = sel_wire[0..0] & data_wire[7..7] # !(sel_wire[0..0]) & data_wire[6..6];
	l1_w0_n4_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[8..8];
	l1_w0_n5_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[10..10];
	l1_w0_n6_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[12..12];
	l1_w0_n7_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[14..14];
	l1_w0_n8_mux_dataout = sel_wire[0..0] & data_wire[17..17] # !(sel_wire[0..0]) & data_wire[16..16];
	l1_w0_n9_mux_dataout = sel_wire[0..0] & data_wire[19..19] # !(sel_wire[0..0]) & data_wire[18..18];
	l2_w0_n0_mux_dataout = sel_wire[1..1] & data_wire[33..33] # !(sel_wire[1..1]) & data_wire[32..32];
	l2_w0_n1_mux_dataout = sel_wire[1..1] & data_wire[35..35] # !(sel_wire[1..1]) & data_wire[34..34];
	l2_w0_n2_mux_dataout = sel_wire[1..1] & data_wire[37..37] # !(sel_wire[1..1]) & data_wire[36..36];
	l2_w0_n3_mux_dataout = sel_wire[1..1] & data_wire[39..39] # !(sel_wire[1..1]) & data_wire[38..38];
	l2_w0_n4_mux_dataout = sel_wire[1..1] & data_wire[41..41] # !(sel_wire[1..1]) & data_wire[40..40];
	l2_w0_n5_mux_dataout = sel_wire[1..1] & data_wire[43..43] # !(sel_wire[1..1]) & data_wire[42..42];
	l2_w0_n6_mux_dataout = sel_wire[1..1] & data_wire[45..45] # !(sel_wire[1..1]) & data_wire[44..44];
	l2_w0_n7_mux_dataout = sel_wire[1..1] & data_wire[47..47] # !(sel_wire[1..1]) & data_wire[46..46];
	l3_w0_n0_mux_dataout = sel_wire[2..2] & data_wire[49..49] # !(sel_wire[2..2]) & data_wire[48..48];
	l3_w0_n1_mux_dataout = sel_wire[2..2] & data_wire[51..51] # !(sel_wire[2..2]) & data_wire[50..50];
	l3_w0_n2_mux_dataout = sel_wire[2..2] & data_wire[53..53] # !(sel_wire[2..2]) & data_wire[52..52];
	l3_w0_n3_mux_dataout = sel_wire[2..2] & data_wire[55..55] # !(sel_wire[2..2]) & data_wire[54..54];
	l4_w0_n0_mux_dataout = sel_wire[3..3] & data_wire[57..57] # !(sel_wire[3..3]) & data_wire[56..56];
	l4_w0_n1_mux_dataout = sel_wire[3..3] & data_wire[59..59] # !(sel_wire[3..3]) & data_wire[58..58];
	l5_w0_n0_mux_dataout = sel_wire[4..4] & data_wire[61..61] # !(sel_wire[4..4]) & data_wire[60..60];
	data_wire[] = ( l4_w0_n1_mux_dataout, l4_w0_n0_mux_dataout, l3_w0_n3_mux_dataout, l3_w0_n2_mux_dataout, l3_w0_n1_mux_dataout, l3_w0_n0_mux_dataout, l2_w0_n7_mux_dataout, l2_w0_n6_mux_dataout, l2_w0_n5_mux_dataout, l2_w0_n4_mux_dataout, l2_w0_n3_mux_dataout, l2_w0_n2_mux_dataout, l2_w0_n1_mux_dataout, l2_w0_n0_mux_dataout, l1_w0_n15_mux_dataout, l1_w0_n14_mux_dataout, l1_w0_n13_mux_dataout, l1_w0_n12_mux_dataout, l1_w0_n11_mux_dataout, l1_w0_n10_mux_dataout, l1_w0_n9_mux_dataout, l1_w0_n8_mux_dataout, l1_w0_n7_mux_dataout, l1_w0_n6_mux_dataout, l1_w0_n5_mux_dataout, l1_w0_n4_mux_dataout, l1_w0_n3_mux_dataout, l1_w0_n2_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]);
	result[] = ( l5_w0_n0_mux_dataout);
	sel_wire[] = ( sel[4..0]);
END;
--VALID FILE