mux_lpc.tdf

微程序模拟CPU实现加减与或异或转移储存等功能。

--lpm_mux CASCADE_CHAIN="IGNORE" DEVICE_FAMILY="Stratix II" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=16 LPM_WIDTH=1 LPM_WIDTHS=4 data result sel
--VERSION_BEGIN 7.2 cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ  VERSION_END


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--synthesis_resources = lut 5 
SUBDESIGN mux_lpc
( 
	data[15..0]	:	input;
	result[0..0]	:	output;
	sel[3..0]	:	input;
) 
VARIABLE
	l1_w0_n0_mux_dataout	:	WIRE;
	l1_w0_n1_mux_dataout	:	WIRE;
	l1_w0_n2_mux_dataout	:	WIRE;
	l1_w0_n3_mux_dataout	:	WIRE;
	l1_w0_n4_mux_dataout	:	WIRE;
	l1_w0_n5_mux_dataout	:	WIRE;
	l1_w0_n6_mux_dataout	:	WIRE;
	l1_w0_n7_mux_dataout	:	WIRE;
	l2_w0_n0_mux_dataout	:	WIRE;
	l2_w0_n1_mux_dataout	:	WIRE;
	l2_w0_n2_mux_dataout	:	WIRE;
	l2_w0_n3_mux_dataout	:	WIRE;
	l3_w0_n0_mux_dataout	:	WIRE;
	l3_w0_n1_mux_dataout	:	WIRE;
	l4_w0_n0_mux_dataout	:	WIRE;
	data_wire[29..0]	: WIRE;
	sel_wire[3..0]	: WIRE;

BEGIN 
	l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[1..1] # !(sel_wire[0..0]) & data_wire[0..0];
	l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[3..3] # !(sel_wire[0..0]) & data_wire[2..2];
	l1_w0_n2_mux_dataout = sel_wire[0..0] & data_wire[5..5] # !(sel_wire[0..0]) & data_wire[4..4];
	l1_w0_n3_mux_dataout = sel_wire[0..0] & data_wire[7..7] # !(sel_wire[0..0]) & data_wire[6..6];
	l1_w0_n4_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[8..8];
	l1_w0_n5_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[10..10];
	l1_w0_n6_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[12..12];
	l1_w0_n7_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[14..14];
	l2_w0_n0_mux_dataout = sel_wire[1..1] & data_wire[17..17] # !(sel_wire[1..1]) & data_wire[16..16];
	l2_w0_n1_mux_dataout = sel_wire[1..1] & data_wire[19..19] # !(sel_wire[1..1]) & data_wire[18..18];
	l2_w0_n2_mux_dataout = sel_wire[1..1] & data_wire[21..21] # !(sel_wire[1..1]) & data_wire[20..20];
	l2_w0_n3_mux_dataout = sel_wire[1..1] & data_wire[23..23] # !(sel_wire[1..1]) & data_wire[22..22];
	l3_w0_n0_mux_dataout = sel_wire[2..2] & data_wire[25..25] # !(sel_wire[2..2]) & data_wire[24..24];
	l3_w0_n1_mux_dataout = sel_wire[2..2] & data_wire[27..27] # !(sel_wire[2..2]) & data_wire[26..26];
	l4_w0_n0_mux_dataout = sel_wire[3..3] & data_wire[29..29] # !(sel_wire[3..3]) & data_wire[28..28];
	data_wire[] = ( l3_w0_n1_mux_dataout, l3_w0_n0_mux_dataout, l2_w0_n3_mux_dataout, l2_w0_n2_mux_dataout, l2_w0_n1_mux_dataout, l2_w0_n0_mux_dataout, l1_w0_n7_mux_dataout, l1_w0_n6_mux_dataout, l1_w0_n5_mux_dataout, l1_w0_n4_mux_dataout, l1_w0_n3_mux_dataout, l1_w0_n2_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]);
	result[] = ( l4_w0_n0_mux_dataout);
	sel_wire[] = ( sel[3..0]);
END;
--VALID FILE